Analysis of frequency-dependent series resistance and interface states of In/SiO2/p-Si (MIS) structures

In this work, the investigation of the interface state density and series resistance from capacitance–voltage (C–V) and conductance–voltage (G/ω−V) characteristics in In/SiO₂/p-Si metal–insulator–semiconductor (MIS) structures with thin interfacial insulator layer have been reported. The thickness of SiO₂ film obtained from the measurement of the oxide capacitance corrected for series resistance in the strong accumulation region is 220 Å. The forward and reverse bias C–V and G/ω−V characteristics of MIS structures have been studied at the frequency range 30 kHz–1 MHz at room temperature. The frequency dispersion in capacitance and conductance can be interpreted in terms of the series resistance (R_s) and interface state density (D_it) values. Both the series resistance R_s and density of interface states D_it are strongly frequency-dependent and decrease with increasing frequency. The distribution profile of R_s–V gives a peak at low frequencies in the depletion region and disappears with increasing frequency. Experimental results show that the interfacial polarization contributes to the improvement of the dielectric properties of In/SiO₂/p-Si MIS structures. The interface state density value of In/SiO₂/p-Si MIS diode calculated at strong accumulation region is 1.11×10¹² eV⁻¹ cm⁻² at 1 MHz. It is found that the calculated value of D_it (≈10¹² eV⁻¹ cm⁻²) is not high enough to pin the Fermi level of the Si substrate disrupting the device operation.     

Controlling the electrical characteristics of Al/p-Si structures through Bi4Ti3O12 interfacial layer

In this study, the effects of high permittivity interfacial Bi₄Ti₃O₁₂ (BTO) layer deposition on the main electrical parameters; such as barrier height, series resistance, rectifying ratio, interface states and shunt resistance, of Al/p-Si structures are investigated using the current–voltage (I–V) and admittance measurements (capacitance–voltage, C–V and conductance–voltage, G/ω–V) at 1 MHz and room temperature. I–V characteristics revealed that, due to BTO layer deposition, series resistance values that were calculated by both Ohm's law and Cheung's method decreased whereas shunt resistance values increased. Therefore, leakage current value decreased significantly by almost 35 times as a result of high permittivity interfacial BTO layer. Moreover, rectifying ratio was improved through BTO interfacial layer deposition. I–V data indicated that high permittivity interfacial BTO layer also led to an increase in barrier height. Same result was also obtained through C–V data. Obtained results showed that the performance of the device is considerably dependent on high permittivity BTO interfacial layer.     

Influence of X-irradiation on the solicon-silicon dioxide interface of MOS structures

Silicon MOS structures with an SiO₂−Si₃N₄ insulator were exposed to X-rays. Positive oxide charges arise and the continuous density of fast states increases at the Si−SiO₂ interface. In addition, a single energy state develops above the middle of the energy gap atE−E _v=600 meV. Annealing measurements in dry air and H₂ lead to the conclusion that the single energy level originates from a dissociated hydrogen bond in the silicon dioxide.     

Equivalent distributed capacitance model of oxide traps on frequency dispersion of C-V curve for MOS capacitors

An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C-V curve of MOS capacitors measured for a frequency range from 1 kHz to1 MHz.The proposed model is based on the Fermi-Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal.The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data.Simulations indicate thatthe capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface,with negligible effects from the traps far from the interface,and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed.In addition,by excluding the negligible effect of oxide-trap conductance,the model avoids the use of imaginary numbers and complex calculations,and thus is simple and intuitive.     

Ⅲ族元素掺杂对SnO2电子结构及电学性能的影响

采用密度泛函理论研究了Ⅲ族元素掺杂对SnO2电子结构及电学性能的影响.态密度分析结果表明,以替代位存在的Ⅲ族杂质均使SnO2的费米能级明显向低能态方向移动,使得价带顶不完全填满,因此在SnO2中均充当受主作用.部分态密度分析结果表明,相对于掺Al的SnO2,Ⅲ族元素中的Ga及In对费米能级附近态密度贡献较大,其主要贡献来自Ga3d态或In4d态,这预示着在SnO2中掺Ga或In能实现更好的p型掺杂效果.电离能计算结果进一步表明,在Al,Ga及In三种元素中,替位In有最小的电离能(0.06 eV),这说明其在SnO2中能形成最浅的受主能级,因而在同等掺杂情况下,可引入最高浓度的空穴,从而实现最佳的p型掺杂效果.     

Characterization of metal/GaN Schottky interfaces based on I–V–T characteristics

Interface properties of metal/n- and p-GaN Schottky diodes are studied by I–V–T and C–V–T measurements, and simulation of their characteristics. On the basis of the previously proposed “surface patch” model, the gross behavior of I–V–T characteristics, which includes Richardson plots together with temperature dependence of the effective Schottky barrier heights (SBHs) and n-values, can be well reproduced. Furthermore, the dependence of the true SBH on the metal work function was also deduced from high-temperature I–V curves, giving S-values of 0.28 and 0.20 for n- and p-GaN samples, respectively, and the interface Fermi level tends to be pinned at a characteristic energy of about two-third of the bandgap.     

The importance of the series resistance in calculating the characteristic parameters of the Schottky contacts

Cd/p-Si Schottky barrier diodes (SBDs) with and without the native oxide layer have been fabricated to determine the importance of the fact that the series resistance value is considered in calculating the interface state density distribution (ISDD) from the forward bias current-voltage (I-V) characteristics of the Cd/p-Si SBDs. The statistical analysis yielded mean values of 0.71 ± 0.02 eV and 1.24 ± 0.12 for the BH and ideality factor of the Cd/p-Si SBDs (15 dots) without the native oxide layer (MS), respectively, and mean values of 0.79 ± 0.02 eV and 1.36 ± 0.06 eV for the Cd/p-Si SBDs (28 dots) with the native oxide layer (metal-insulating layer-semiconductor (MIS)). The interface state density (Nss) distributions of the devices were calculated taking into account their series resistance values. At the same energy position near the top of the valence band, the interface state density values without taking into account the series resistance value of the devices are almost one order of magnitude larger than Nss obtained taking into account series resistance value.     

Effect of energy distribution of interface states on the electrical characteristics of semiconductor heterojunction diode

An energy distribution of interface states has been considered to study the electrical characteristics of an anisotype semiconductor heterojunction. Various electrical quantities such as the surface potential, current, conductance and ideality factor of the device have been studied. The current-voltage and conductance-voltage characteristics are found largely sensitive to the parameters controlling the distribution profile of interface states. A new expression for the ideality factor of the device has been derived, which predicts appreciable voltage dependence due to the distributive nature of the interface states. It has been found that the experimental I-V data of p-InP/n-CdS heterojunction reported by earlier workers can be satisfactorily explained with the help of the present model if the effect of shunt resistance of the device is included in the evaluation scheme.     

Effect of a quantizing magnetic field on the capacitance of MOS structures of small-gap semiconductors

An attempt is made to investigate the effect of a quantizing magnetic field on the capacitance of MOS structures of small-gap semiconductors havingn-channel inversion layers under the weak electric-field limit. It is found, takingn-channel InSb as an example, that both the MOS and surface capacitances show spiky oscillations with changing magnetic field. It is further observed that the sharpness and the depths of the spikes increase with increasing magnetic field whereas the depths are found to decrease with increasing thickness of the insulating layer. On leave of absence from the Department of Physics, Patna University, Patna, India     

The role of multiple damaged layers at the Si/SiO2 interface on the dielectric breakdown of MOS capacitors

Oxide breakdown in metal-oxide-semiconductor (MOS) devices in the nanometer scale is simulated as a cluster growth depending process in which the local electric field is a function of a randomly varying local dielectric permissivity. Effects of MOS device bias polarity, film thickness and non-uniform defect distributions through the entire oxide film on the breakdown are studied. The slope of the Weibull distribution increases with the oxide thickness in agreement with experimental results.     

Forward and reverse bias current-voltage characteristics of Au/n-Si Schottky barrier diodes with and without SnO2 insulator layer

The effects of interfacial insulator layer, interface states (N_ss) and series resistance (R_s) on the electrical characteristics of Au/n-Si structures have been investigated using forward and reverse bias current-voltage (I-V) characteristics at room temperature. Therefore, Au/n-Si Schottky barrier diodes (SBDs) were fabricated as SBDs with and without insulator SnO₂ layer to explain the effect of insulator layer on main electrical parameters. The values of ideality factor (n), R_s and barrier height (Φ_Bo) were calculated from ln(I) vs. V plots and Cheung methods. The energy density distribution profile of the interface states was obtained from the forward bias I-V data by taking bias dependence of ideality factor, effective barrier height (Φ_e) and R_s into account for MS and MIS SBDs. It was found that N_ss values increase from at about mid-gap energy of Si to bottom of conductance band edge of both SBDs and the MIS SBD’s N_ss values are 5-10 times lower than those of MS SBD’s. An apparent exponential increase from the mid-gap towards the bottom of conductance band is observed for both SBDs’ (MS and MIS) interface states obtained without taking R_s into account.     

表面结构对SnO2半导体纳米粒子荧光性质的影响

本文利用荧光光谱对ＳｎＯ２纳米粒子水溶胶及其有机溶胶的光学性质进行了研究。发现粒子的表面结构对其光学性质具有极大的影响。水溶胶的荧光发射是由氧空位控制的,其发射强度工;有机溶胶由于表面活性剂的作用,改变粒子的表面结构,得到较强的荧光发射。     

Effect of annealing on the electronic parameters of Au/poly(ethylmethacrylate)/n-InP Schottky diode with organic interlayer

A thin poly(ethylmethacrylate) (PEMA) layer is deposited on n-InP as an interlayer for electronic modification of Au/n-InP Schottky structure. The electrical properties of Au/PEMA/n-InP Schottky diode have been investigated by current–voltage (I–V) and capacitance–voltage (C–V) measurements at different annealing temperatures. Experimental results show that Au/PEMA/n-InP structure exhibit a good rectifying behavior. An effective barrier height as high as 0.83 eV (I–V) and 1.09 eV (C–V) is achieved for the Au/PEMA/n-InP Schottky structure after annealing at 150 °C compared to the as-deposited and annealed at 100 and 200 °C. Modified Norde's functions and Cheung method are also employed to calculate the barrier height, series resistance and ideality factors. Results show that the barrier height increases upon annealing at 150 °C and then slightly decreases after annealing at 200 °C. The PEMA layer increases the effective barrier height of the structure as this layer creates a physical barrier between the Au metal and the n-InP. Terman's method is used to determine the interface state density and it is found to be 5.141 × 10¹² and 4.660 × 10¹² cm^?2 eV^?1 for the as-deposited and 200 °C annealed Au/PEMA/n-InP Schottky diodes. Finally, it is observed that the Schottky diode parameters change with increasing annealing temperature.     

Mn-N共掺杂SnO2电子结构的第一性原理研究

基于第一性原理方法研究了Mn,N单掺SnO2及Mn-N共掺SnO2的能带结构以及态密度。研究结果表明：单掺和共掺均能使带隙值降低,态密度能量向低能级方向移动,费米能级附近出现杂质能级,材料导电性增强。Mn-N共掺SnO2材料与Mn单掺相比价带顶和导带顶能级出现分离,带隙中出现的杂质能级更多,Mn的分波态密度更加弥散, Mn-N共掺使Mn的掺入更加容易。     

Impact of O_2 post oxidation annealing on the reliability of SiC/SiO_2 MOS capacitors

The effects of dry O_2 post oxidation annealing(POA) at different temperatures on SiC/SiO_2 stacks are comparatively studied in this paper. The results show interface trap density(Dit) of SiC/SiO_2 stacks, leakage current density(Jg), and time-dependent dielectric breakdown(TDDB) characteristics of the oxide, are affected by POA temperature and are closely correlated. Specifically, Dit, Jg, and inverse median lifetime of TDDB have the same trend against POA temperature, which is instructive for SiC/SiO_2 interface quality improvement. Moreover, area dependence of TDDB characteristics for gate oxide on SiC shows different electrode areas lead to same slope of TDDB Weibull curves.     

Effect of displacement on resistance and capacitance of polyaniline film

This paper investigates the properties of displacement sensors based on polyaniline (PANI) films. About 1 wt% of PANI micropowder is mixed and stirred in a solution of 90 wt% water and 10 wt% alcohol at room temperature. The films of PANI are deposited from solution by drop-casting on Ag electrodes,which are preliminary deposited on glass substrates. The thicknesses of the PANI films are in the range of 20 μm-80 μm. A displacement sensor with polyaniline film as an active material is designed and fabricated. The investigations showed that,on average,the AC resistance of the sensor decreases by 2 times and the capacitance accordingly increases by 1.6 times as the displacement changes in the range of 0 mm-0.5 mm. The polyaniline is the only active material of the displacement sensor. The resistance and capacitance of the PANI changes under the pressure of spring and elastic rubber,and this pressure is created by the downward movement of the micrometer.     

基于电容和电导特性分析GaN蓝光发光二极管老化机理

采用正向交流小信号方法测试和分析老化前后GaN发光二极管（LED）的电容-电压特性,结合串联电阻、理想因子、隧穿电流参数讨论负电容以及电导变化情况.基于L-V曲线定性分析老化前后负电容的阈值电压,老化之后样管的受主浓度降低,辐射复合概率下降,大量缺陷以及非辐射复合中心出现,对载流子俘获作用增强,造成负电容降低.反向偏压以及小正向偏压下,隧穿效应导致老化之后样管的电导增大;正向偏压大于2.2 V区域,考虑串联电阻效应,老化后样管电导减小.在分析LED电容-电压、光输出、电学特性曲线与老化机理基础上,通过实验论证以及理论解释表明,负电容以及电导特性可作为分析LED老化特性的参考依据. 关键词： GaN发光二极管 负电容 电导 老化机理     

Influence of the thickness of the tunnel layer on the charging characteristics of Si nanocrystals embedded in an ultra-thin SiO2 layer

In this paper, we have studied the effect of the thickness of the initial SiO₂ layer (5–7 nm) on the charge and discharge properties of a 2D array of Si nanoparticles embedded in these SiO₂ layers fabricated by ultra-low-energy ion implantation (ULE-II) and annealing. The structural characteristics of these nanocrystal-based memories (position of the nanocrystals with respect to the electrodes, size and surface density of the particles in the plane) were studied by transmission electron microscopy (TEM) and energy filtered TEM (EF-TEM). Electrical characterizations were performed at room temperature using a nano-MOS capacitor to be able to address only a few nanoparticles (nps). EFTEM gives the measurements of oxide thickness, injection, control and nps distances, size and density. I–V and I–t measurements exhibit current peaks and random telegraph signal fluctuations that can be interpreted as due to quantized charging of the nps and to some electrostatic interactions between the trapped charges and the tunnelling current. We have shown that these characteristics strongly vary with the initial oxide thickness, exhibiting several charging/discharging events for the 7-nm-thick layer while charging events prevail in the case of 5-nm-thick layer. These results indicate that the probability of discharging phenomena is reduced when the tunnel layer thickness decreases.     

On the profile of temperature dependent electrical and dielectric properties of Au/SiO2/n-GaAs (MOS) structures at various frequencies

The temperature (T) dependence of electrical and dielectric characteristics such as series resistance (R_s), dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tan δ), and real and imaginary part of electrical modulus (M′ and M″) of the Au/SiO2/n-GaAs (MOS) structures have been investigated in the temperature range of 80–350 K at various frequencies by using experimental capacitance (C) and conductance (G/w) measurements. Experimental results show that both C and G/w characteristics were quite sensitive to frequency and temperature at especially high temperatures and low frequencies due to a continuous density distribution of interface states and their relaxation time, and thermal restructuring and reordering of the interface. Series resistance values of this device obtained from Nicollian method decrease with increasing frequency and temperature. The ε′, ε″, tan δ, and M′ and M″ were found a strong function of frequency and temperature. While the values of ε′, ε″, and tan δ decrease, M′ and M″ increase with increasing frequency. Also, while ε′ and ε″ increase, M′ and M″ decrease with increasing temperature. The tan δ and M′ values are almost independent temperature especially at high frequencies (f≥500 kHz).     

Effect of the Landau level broadening on the quantum Hall conductance

Summary In a previous paper, Kliroset al. presented a model calculation of the Hall conductivity as a function of the Landau level broadening Γ for finite temperatures. In this paper, the effect of Landau-level broadening on the structure of the Hall conductivity is investigated. The experimental data regarding the Si-MOSFET and GaAs-heterostructure experiments are reproduced including a functional dependence of Γ on the magnetic field. The influence of the effectiveg-factor is considered as well.