Device and performance parameters of Cu(In,Ga)(Se,S)2-based solar cells with varying i-ZnO layer thickness

In pursuit of low-cost and highly efficient thin film solar cells, Cu(In,Ga)(Se,S)₂/CdS/i-ZnO/ZnO:Al (CIGSS) solar cells were fabricated using a two-step process. The thickness of i-ZnO layer was varied from 0 to 454 nm. The current density-voltage (J-V) characteristics of the devices were measured, and the device and performance parameters of the solar cells were obtained from the J-V curves to analyze the effect of varying i-ZnO layer thickness. The device parameters were determined using a parameter extraction method that utilized particle swarm optimization. The method is a curve-fitting routine that employed the two-diode model. The J-V curves of the solar cells were fitted with the model and the parameters were determined. Results show that as the thickness of i-ZnO was increased, the average efficiency and the fill factor (FF) of the solar cells increase. Device parameters reveal that although the series resistance increased with thicker i-ZnO layer, the solar cells absorbed more photons resulting in higher short-circuit current density (J_sc) and, consequently, higher photo-generated current density (J_L). For solar cells with 303-454 nm-thick i-ZnO layer, the best devices achieved efficiency between 15.24% and 15.73% and the fill factor varied between 0.65 and 0.67.     

Effect of SrTiO3 thickness on the capacitance–voltage characteristics of (La,Sr)CoO3/(Pb,La)(Zr,Ti)O3/SrTiO3/LaVO3 epitaxial heterostructures

We report the effect of SrTiO₃ thickness on the capacitance?Cvoltage (C?CV) characteristics of (La,Sr)CoO₃/(Pb,La)(Zr,Ti)O₃/SrTiO₃/LaVO₃ metal?Cferroelectric?Cinsulator?Csemiconductor (MFIS) epitaxial heterostructures. The C?CV measurement of the heterostructure exhibited the asymmetry of capacitance with respect to gate bias. Within the given thickness range (5?C30 nm), the amount of capacitance reduction at positive gate bias and the rapidness of capacitance reduction decreased with increasing SrTiO₃ thickness, which is consistent with the C?CV characteristics of conventional silicon-based MFIS capacitors. These results suggest that quantitative understanding on the electrical behavior of oxide heterostructures is possible with C?CV analysis, with potentially important implications on their device applications.     

Compatibility of glass textures with E-beam evaporated polycrystalline silicon thin-film solar cells

For polycrystalline silicon thin films on glass, E-beam evaporation capable of high-rate deposition of amorphous silicon (a-Si) film precursor up to 1 μm/minute is a potentially low-cost solution to replace the main stream a-Si deposition method—plasma enhanced chemical vapour deposition (PECVD). Due to weak absorption of near infrared light and a target of 2 μm Si absorber thickness, glass substrate texturing as a general way of light trapping is vital to make E-beam evaporation commercially viable. As a result, the compatibility of e-beam evaporation with glass textures becomes essential. In this paper, glass textures with feature size ranging from ～200 nm to ～1.5 micron and root-mean-square roughness (Rms) ranging from ～10 nm to 200 nm are prepared and their compatibility with e-beam evaporation is investigated. This work indicates that e-beam evaporation is only compatible with small smooth submicron sized textures, which enhances J _sc by 21 % without degrading V _oc of the cells. Such textures improve absorption-based J _sc up to 45 % with only 90 nm SiN _x as the antireflection and barrier layer; however, the enhancement degrades to ～10 % with 100 nm SiO _x +90 nm SiN _x as the barrier layer. The absorption-based J _sc is abbreviated by J _sc(A), which is deduced by integrating the multiplication product of the measured absorption and the AM1.5G spectrum in the wavelength range 300–1050 nm assuming unity internal quantum efficiency at each wavelength. This investigation is also relevant to other thin-film solar cell technologies which require evaporating the absorber onto textured substrate/superstrate.     

Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application

In this paper, a gate-all-around junctionless tunnel field effect transistor (JLTFET) based on heterostructure of compound and group III–V semiconductors is introduced and simulated. In order to blend the high tunneling efficiency of narrow band gap material JLTFETs and the high electron mobility of III–V JLTFETs, a type I heterostructure junctionless TFET adopting Ge–Al _x Ga_1?x As–Ge system has been optimized by numerical simulation in terms of aluminum (Al) composition. To improve device performance, we considered a nanowire structure, and it was illustrated that high-performance logic technology can be achieved by the proposed device. The optimal Al composition founded to be around 20 % (x = 0.2). The numerical simulation results demonstrate that the proposed device has low leakage current I _OFF of ~1.9 × 10^?17, I _ON of 4 µA/µm, I _ON/I _OFF current ratio of 1.7 × 10¹¹ and subthreshold swing SS of 12.6 mV/decade at the 40 nm gate length and temperature of 300 K.     

Subthreshold swing characteristics of nanowire tunneling FETs with variation in gate coverage and channel diameter

In this study, we demonstrate the simulated subthreshold swing (SS) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30% to 100%. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS. Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100% exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼10¹³, and an on-current of ∼10⁻⁵ A/μm.     

Detailed analysis of ultrathin fluorescent red dye interlayer for organic photovoltaic cells

The influence of an ultrathin 4-(dicyanomethylene)-2-t-butyl-6-(1,1,7,7-tetramethyljulolidyl-9-enyl)-4H-pyran (DCJTB) fluorescent dye layer at donor/acceptor heterojunction on the performance of small-molecule organic photovoltaic (OPV) cell is studied. The structure of OPV cell is of indium-tin oxide (ITO)/copper phthalocyanine (CuPc)/DCJTB/fullerene (C₆₀)/bathophenanthroline (Bphen)/Ag. The results show that open circuit voltage (V_OC) increases to 0.57 V as the film thickness of DCJTB layer increases from 0.2 to 2.0 nm. By using an equivalent circuit model, the enhancement of V_OC is found to be attributed to the reduced reverse saturation current density (J_S) which is due to the lower highest occupied molecular orbital (HOMO) level in DCJTB than that in CuPc. Also, the short circuit current density (J_SC) is affected when the DCJTB layer becomes thicker, resulting from the high series resistance R_SA due to the low charge carrier mobility of fluorescent red dye.     

Trap-controlled behavior in ultrathin Lu2O3 high-k gate dielectrics

Amorphous Lu₂O₃ high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu₂O₃ film has amorphous structure and the interface with Si substrate is free from amorphous SiO₂. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10⁻⁵ A/cm² at 1 V accumulation bias was obtained for 4.5 nm thick Lu₂O₃ thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance-voltage (C-V) and current density-voltage (J-V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.     

High performance Zn–Sn–O thin film transistors with Cu source/drain electrode

Zn–Sn–O (ZTO) thin film transistors (TFTs) were fabricated with a Cu source/drain electrode. Although a reasonably high mobility (μ_FE) of 13.2 cm²/Vs was obtained for the ZTO TFTs, the subthreshold gate swing (SS) and threshold voltage (V_th) of 1.1 V/decade and 9.1 V, respectively, were inferior. However, ZTO TFTs with Ta film inserted as a diffusion barrier, exhibited improved SS and V_th values of 0.48 V/decade and 3.0 V, respectively as well as a high μ_FE value of 18.7 cm²/Vs. The improvement in the Ta‐inserted device was attributed to the suppression of Cu lateral diffusion into the ZTO channel region. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Influence of heat treatment process in In<Subscript>2</Subscript>O<Subscript>3</Subscript>-MWCNTs as photoanode in DSSCs

Indium oxide-multi-walled carbon nanotubes (In₂O₃-MWCNTs) were prepared by sol-gel method for DSSCs. The synthesis of indium oxide (In₂O₃) was carried out by dissolving indium chloride (InCl₃) in a solvent of 2-methoxyethanol. Different annealing temperatures of 400, 450, 500, 550, and 600 °C were proposed in this study. The changes in the structural properties were analyzed by means of X-ray diffraction (XRD) and atomic force microscopy (AFM) analysis. The XRD spectrum estimated the average crystallite sizes of 3 nm for each sample. AFM results indicated very rough surface area of the films where it increased linearly from 1.8 to 11 nm as the annealing temperature increases. The In₂O₃-MWCNTs-based DSSC exhibited good photovoltaic performance with power conversion efficiency (η), photocurrent density (J _sc ), open circuit voltage (V _oc ), and fill factor (FF) of 1.13 %, 5.5 mA/cm², 0.53 V, and 0.42, respectively. Even though the film annealed at 450 °C exhibited low τ _eff, it achieved the greatest D _eff of 29.67 cm² s^?1 which provides an efficient pathway for the photogenerated electrons with minimum electron recombination loss that increased the J _sc and V _oc in the DSSC. The obtained structural and electron transport analysis was proposed as a suitable benchmark for In₂O₃-MWCNTs-based dye-sensitized solar cell (DSSCs) application. Hence, this study suggests that the optimum temperature for In₂O₃-MWCNTs is at annealing temperature of 450 °C prepared via sol-gel method.     

Doping level and environment dependence of structural stability and magnetic properties in Mn-doped WS2 bilayer in first principles

We carried out first-principles electronic structure calculation to study the structural stability and magnetic properties of Mn-doped WS₂ ultra-thin films within the density functional theory. Adopting various configurations of Mn doping into WS₂ bilayer, we find that the magnetic phase can be manipulated among the ferromagnetic, antiferromagnetic, or ferrimagnetic phases by altering doping level and growth environment. Magnetic phase and strength are determined by magnetic coupling of Mn dopants 3d electrons which can be attributed crucially to the exchange interaction mediated by neighboring S atoms 3p electrons. Accompanying to the magnetic phase transition, the electronic structure reveals that transport properties switch from semiconducting with various bandgap to half-metallic states. This result implicates possible way to develop magnetic semiconductors based on Mn doped 2D WS₂ ultra-thin films for spintronics applications.     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

Improved performance of InGaZnO thin-film transistors with Ta2O5/Al2O3 stack deposited using pulsed laser deposition

Ta₂O₅/Al₂O₃ stacked thin film was fabricated as the gate dielectric for low-voltage-driven amorphous indium–gallium–zinc-oxide (IGZO) thin film transistors (TFTs). The Ta₂O₅/Al₂O₃ stacked thin film exhibits a combination of the advantages of Al₂O₃ and Ta₂O₅. The IGZO TFT with Ta₂O₅/Al₂O₃ stack exhibits good performance with large saturation mobility of 26.66 cm² V⁻¹ s⁻¹, high on/off current ratio of 8 × 10⁷, and an ultra-small subthreshold swing (SS) of 78 mV/decade. Such small SS value is even comparable with that of submicrometer single-crystalline Si MOSFET.     

Theoretical simulation of photovoltaic response of graphene-on-semiconductors

Using the fundamental models for voltage and current, we report on the photovoltaic behavior of graphene-on-semiconductor-based devices. The graphene-n-Si and graphene-n-GaAs systems are studied for open-circuit voltage (V _OC) and short-circuit current density (J _SC) under low- and high-level injection conditions. The effects of semiconductor doping density and surface recombination velocity on the V _OC of both systems are investigated. The V _OC for graphene-n-Si under low- and high-level injection conditions are found to be 0.353 V and 0.451 V, respectively, whereas the V _OC for graphene-n-GaAs under low- and high-level injection conditions are 0.441 V and 0.471 V, respectively. The J _SC for graphene-n-Si under low- and high-level injection conditions are calculated as 3 mAcm^?2 and 4.78 mAcm^?2, respectively, whereas the J _SC for graphene-n-GaAs under low- and high-level injection conditions are 5.2 mAcm^?2 and 6.68 mAcm^?2, respectively. These results are in good agreement with the reported experimental work.     

Current-voltage dependencies of heterogeneous semiconductor systems

Computed current-voltage (J–V) dependencies of heterogeneous (powder) semiconductor systems reveal an anomalous dependence between the constant-voltage current J and the uncompensated donor (acceptor) concentration N. Over a range of N(N₁ < n < N₂) of approximately one decade, J decreases by as much as four decades with increasing N. For N > N₂, the grain Schottky barrier thickness d is less than the grain half-width l/2, the grain surface potential V_s is almost independent of N and the J–V dependence is superlinear. For N₁ < N < N₂, d > l/2, V_s decreases linearly with N, J increases strongly with decreasing N and the J–V dependence is superlinear. For N < N₁, d > l/2. V_s ? V_th ( = kT/q) and J ∝ NV. The phenomenon is used to account for some observed J–V dependencies with column II-chalcogenide and ZnO powder semiconductor systems (electro-optic displays, electrophotographic receptors and heterogeneous catalysts).     

Polycrystalline GaSb films prepared by the coevaporation technique

Gallium antimonide (GaSb) films were deposited onto fused silica and n-Si (100) substrates by coevaporating Ga and Sb from appropriate evaporation sources. The films were polycrystalline in nature. The size and the shape of the grains varied with the change in the substrate temperature during deposition. The average surface roughness of the films was estimated to be 10 nm. Grain boundary trap states varied between 2×10¹² and 2.2×10¹² cm^?2 while barrier height at the grain boundaries varied between 0.09 eV and 0.10 eV for films deposited at higher temperatures. Stress in the films decreased for films deposited at higher temperatures. XPS studies indicated two strong peaks located at ～543 eV and ～1121 eV for Sb 3d_3/2 and Ga 2p_3/2 core-level spectra, respectively. The PL spectra measured at 300 K was dominated by a strong peak located ～0.55 eV followed by two low intensity peaks ～0.63 eV and 0.67 eV. A typical n-Si/GaSb photovoltaic cell fabricated here indicated V _oc～311 mV and J～29.45 mA/cm², the density of donors (N _d)～3.87×10¹⁵ cm^?3, built in potential (V _bi)～0.48 V and carrier life time (τ)～28.5 ms. Impedance spectroscopy measurements indicated a dielectric relaxation time ～100 μs.     

Transport current density of (Bi1.6Pb0.4)Sr2Ca2Cu3O10 superconductor added with different nano-sized ZnO

The (Bi_1.6Pb_0.4)Sr₂Ca₂Cu₃O₁₀ZnO _x (x=0–0.05 wt%) superconductor with addition of ZnO with average particle size 6 nm and 30 nm was prepared using the co-precipitation method. The ZnO particle size was larger than the coherence length, ξ, and smaller than the penetration depth, λ, of the superconductor. The microstructure, transition temperature (T _c) and transport critical current density (J _c) were studied. SEM micrographs showed a homogeneous distribution of ZnO nanoparticles throughout the samples. J _c of all the ZnO added samples were higher than the non-ZnO added sample. The maximal J _c and T _c were observed when x=0.02 wt% for both series. J _c (77 K) of the 6-nm ZnO added sample was 46 times larger than the non-ZnO added sample. The 6-nm ZnO added sample also showed higher J _c compared to the 30-nm ZnO added sample. ZnO with size closer to ξ was more effective in enhancing J _c.     

Structural characterization of Mg substituted on A/B sites in $$\hbox {NiFe}_2\hbox {O}_4$$ nanoparticles using autocombustion method

A compact quantitative model based on oxide semiconductor interface density of states (DOS) is proposed for Al_0.25Ga_0.75N/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT). Mathematical expressions for surface potential, sheet charge concentration, gate capacitance and threshold voltage have been derived. The gate capacitance behaviour is studied in terms of capacitance–voltage (CV) characteristics. Similarly, the predicted threshold voltage (V _T) is analysed by varying barrier thickness and oxide thickness. The positive V _T obtained for a very thin 3 nm AlGaN barrier layer enables the enhancement mode operation of the MOSHEMT. These devices, along with depletion mode devices, are basic constituents of cascode configuration in power electronic circuits. The expressions developed are used in conventional long-channel HEMT drain current equation and evaluated to obtain different DC characteristics. The obtained results are compared with experimental data taken from literature which show good agreement and hence endorse the proposed model.     

Band diagram determination of MOS structures with different gate materials on 3C-SiC substrate

MOS capacitors were fabricated on 3C-SiC n-type substrate (001) with a 10-μm N-type epitaxial layer. An SiO₂ layer of the thickness t_OX ≈55 nm was deposited by PECVD. Circular Al, Ni, and Au gate contacts 0.7 mm in diameter were formed by ion beam sputtering and lift-off. Energy band diagrams of the MOS capacitors were determined using the photoelectric, electric, and optical measurement methods. Optical method (ellipsometry) was used to determine the gate and dielectric layer thicknesses and their optical indices: the refraction n and the extinction k coefficients. Electrical method of C = f(V_G) characteristic measurements allowed to determine the doping density ND and the flat band voltage VFB in the semiconductor. Most of the parameters which were necessary for the construction of the band diagrams and for determination of the basic physical properties of the structures (e.g. the effective contact potential difference ϕ_MS) were measured by several photoelectric methods and calculated using the measurement data. As a result, complete energy band diagrams have been determined for MOS capacitors with three different gate materials and they are demonstrated for two different gate voltages VG: for the flat-band in the semiconductor (V_G = V_FB) and for the flat-band in the dielectric (V_G = V_G0).     

Effect of poly silicon thickness on the formation of Ni-FUSI gate by using atomic layer deposited nickel film

The effect of poly-Si thickness on silicidation of Ni film was investigated by using X-ray diffraction, auger electron spectroscopy, cross-sectional scanning transmission electron microscopy, resistivity, I–V, and C–V measurements. The poly-Si films with various thickness of 30–200 nm were deposited by LPCVD on thermally grown 50 nm thick SiO₂, followed by deposition of Ni film right after removing the native oxide. The Ni film was prepared by using atomic layer deposition with a N²-hydroxyhexafluoroisopropyl-N¹ (Bis-Ni) precursor. Rapid thermal process was then applied for a formation of fully silicide (FUSI) gate at temperature of 500 °C in N₂ ambient during 30 s. The resultant phase of Ni-silicide was strongly dependent on the thickness of poly-Si layer, continuously changing its phase from Ni-rich (Ni₃Si₂) to Si-rich (NiSi₂) with increasing the thickness of the poly-Si layer, which is believed to be responsible for the observed flat band voltage shift, ΔV_FB, in C–V curves.     

Oriented ZnO nanotubes arrays decorated with TiO2 nanoparticles for dye-sensitized solar cell applications

Dye-sensitized solar cells (DSSCs) based on a novel composite photoanode of TiO₂ nanoparticles coating on electrodeposited ZnO nanotube arrays are fabricated and characterized. An efficiency of 3.94 % is achieved for the composite cell, increasing 86.7 % than 2.11 % of the ZnO nanotubes cell. The short-circuit current (J _sc) and open-circuit voltage (V _oc) are also enhancing 52.9 % and 25.3 %, respectively. The improvements are because of the high surface area of TiO₂ nanoparticles, as well as fast electron transport and light scattering effect of ZnO nanotubes.