基于FPGA视频合成系统设计与实现

为实现将输入的六路BT656视频无失真地合并成一路BT1120视频输出,采用将FPGA技术和视频合成系统相结合的设计方法,用verilog语言设计完成有效视频数据的抽取、SRAM乒乓操作以及FPGA对于视频的拼接处理方法。该系统由视频输入解码模块、存储模块、输出解码模块、i2c模块以及时钟管理模块组成。经算法仿真和逻辑综合,该设计可以实现视频合成的基本功能,满足视频监控系统的实时性要求.综合结果表明该设计占用FPGA片上逻辑资源少,系统运行频率高。     

使用TensorRT进行深度学习推理

TensorRT是一个高性能的深度学习推理平台。它包括一个深度学习推理优化器和运行时为深度学习推理应用程序提供低延迟和高吞吐量。给出了一个使用TensorRT快速构建计算管道的例子,实现通过TensorRT执行智能视频分析的典型应用。该示例演示了使用片上解码器进行解码、使用片上标量进行视频缩放和GPU计算的4个并发视频流。为了演示的简单性，只有一个通道使用NVIDIA TensorRT执行对象标识，并在标识的对象周围生成包围框。该示例还使用视频转换器函数进行各种格式转换，使用EGLImage来演示缓冲区共享和图像显示。最后采用GPU卡V100对ResNet网络进行TensorRT加速性能的实际测试,结果表明TensorRT能够使吞吐量提升大约15倍。     

Wavelength division multiplexed loop buffer memory based optical packet switch

Photonic all-optical switching is widely considered as one of the technique to utilize the enormous optical bandwidth. Optical packet switching provides high speed, data rate transparency, data format transparency, efficient use of bandwidth and flexibility. To resolve the conflict during contention, packets are needed to be buffered. Due to the lack of optical RAM, fiber delay lines (FDLs) are the most suited option to buffer the packets. This paper proposes new optical packet switch architecture alongwith feedback shared buffer utilizing the advantage of WDM loop buffer memory. The loop buffer module used in this switch architecture is a new approach towards WDM buffering of packets. The mathematical modeling is done to validate the results obtained from simulation.     

Reconfigurable mesh-based inter-chip optical interconnection network for distributed-memory multiprocessor system

A 4×4 reconfigurable mesh-based inter-chip optical interconnection network is reported for distributed-memory multiprocessor system and the experiment confirmed that the data rate in each channel could reach above 3.125 Gbps, which would be a good solution to solve the communication bottlenecks between processors. Each node of this reconfigurable mesh could realize 15 internal connection patterns to complete the interconnections of processors. Besides, this mesh interconnect network via ultra-high bandwidth waveguides embedded in EOPCB can realize flexible multiprocessor system architecture options.     

AWG and EDFA based optical packet switch using feedback shared loop buffer memory

Optical packet switching provides high speed, data rate/format transparency, efficient use of bandwidth and flexibility. The major problem in the implementation of “all-optical” switching is contention which occurs when two or more packets arrive at the same time for the same destination. To resolve the contention, we have proposed an optical packet switch architecture based on WDM loop buffer memory in the feedback configuration. In that architecture, the contending packets are stored in a loop buffer module, and routed in the free time slots. The buffering duration in the recirculating loop is limited by a circulation limit. The analysis was been done to obtain the maximum number of allowed circulations. This paper proposes improved version of that optical packet switch architecture, to increase the number of maximum allowed circulations. The modification is done either by adding an extra erbium doped fiber amplifier (EDFA) in the original switch or by replacing the core space switch with arrayed waveguide grating (AWG). The performance analysis has been done by the simulations.     

基于USB2.0和DirectShow的视频采集系统

介绍了一种视频采集系统的总体设计方案、硬件结构、固件和软件结构的设计。通过对USB2.0协议和CY7C68013芯片的分析和研究,可编程接口(GPIF)能最大限度的发挥USB2.0的带宽,平均数据传输率为28Mbits/s,获得了无须压缩的高速单通道和多通道视频数据传输。通过利用USBMicroStudio高效开发USB驱动和采用WDM/Di rectShow架构,实现了视频的采集和存储。     

Evaluation of Fast Sample Entropy Algorithms on FPGAs: From Performance to Energy Efficiency

Entropy is one of the most fundamental notions for understanding complexity. Among all the methods to calculate the entropy, sample entropy (SampEn) is a practical and common method to estimate time-series complexity. Unfortunately, SampEn is a time-consuming method growing in quadratic times with the number of elements, which makes this method unviable when processing large data series. In this work, we evaluate hardware SampEn architectures to offload computation weight, using improved SampEn algorithms and exploiting reconfigurable technologies, such as field-programmable gate arrays (FPGAs), a reconfigurable technology well-known for its high performance and power efficiency. In addition to the fundamental disclosed straightforward SampEn (SF) calculation method, this study evaluates optimized strategies, such as bucket-assist (BA) SampEn and lightweight SampEn based on BubbleSort (BS-LW) and MergeSort (MS-LW) on an embedded CPU, a high-performance CPU and on an FPGA using simulated data and real-world electrocardiograms (ECG) as input data. Irregular storage space and memory access of enhanced algorithms is also studied and estimated in this work. These fast SampEn algorithms are evaluated and profiled using metrics such as execution time, resource use, power and energy consumption based on input data length. Finally, although the implementation of fast SampEn is not significantly faster than versions running on a high-performance CPU, FPGA implementations consume one or two orders of magnitude less energy than a high-performance CPU.     

Vacuum-gap-based lumped element Josephson parametric amplifier

We propose a lumped element Josephson parametric amplifier with vacuum-gap-based capacitor.The capacitor is made of quasi-floating aluminum pad and on-chip ground.We take a fabrication process compatible with air-bridge technology,which makes our design adaptable for future on-chip integrated quantum computing system.Further engineering the input impedance,we obtain a gain above 20 dB over 162-MHz bandwidth,along with a quasi quantum-limit noise performance.This work should facilitate the development of quantum information processing and integrated superconducting circuit design.     

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor(CMOS) technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size(12 nm) and areal density(1.8×10~(11)/cm~2) of Si-NCs.The program/erase(P/E) speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.     

An interconnect width and spacing optimization model considering scattering effect

As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.     

基于USB总线的离散量接口设计与实现

为了满足航空电子仿真系统对离散量输入输出控制的需求,设计开发了一种基于USB总线的离散量输入输出接口。该接口采用USB芯片CH375完成板卡与主机数据通信,51单片机作为主控制器,CPLD实现地址译码和逻辑控制,光耦和继电器分别为输入和输出隔离器件,具有采集56路光耦输入信号和56路继电器输出信号的功能。论文详细探讨了系统总体设计、硬件实现、软件配置和工作流程,给出了系统硬件的框架结构、软件架构,详细讨论了系统的驱动软件开发。该接口满足不同仿真系统离散量输入输出的需要,具有稳定性高、可热插拔、通道数目可变的特点,在工程应用中收到了很好的效果。     

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth–distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.     

Multi-Hop Question Generation Using Hierarchical Encoding-Decoding and Context Switch Mechanism

Neural auto-regressive sequence-to-sequence models have been dominant in text generation tasks, especially the question generation task. However, neural generation models suffer from the global and local semantic semantic drift problems. Hence, we propose the hierarchical encoding–decoding mechanism that aims at encoding rich structure information of the input passages and reducing the variance in the decoding phase. In the encoder, we hierarchically encode the input passages according to its structure at four granularity-levels: [word, chunk, sentence, document]-level. Second, we progressively select the context vector from the document-level representations to the word-level representations at each decoding time step. At each time-step in the decoding phase, we progressively select the context vector from the document-level representations to word-level. We also propose the context switch mechanism that enables the decoder to use the context vector from the last step when generating the current word at each time-step.It provides a means of improving the stability of the text generation process during the decoding phase when generating a set of consecutive words. Additionally, we inject syntactic parsing knowledge to enrich the word representations. Experimental results show that our proposed model substantially improves the performance and outperforms previous baselines according to both automatic and human evaluation. Besides, we implement a deep and comprehensive analysis of generated questions based on their types.     

A review of aspects relating to the improvement of holographic memory technology

Results of studying a holographic memory to write/read digital data pages are presented. The research has been carried out in Novosibirsk, Russia. Great attention was paid to methods of improving recording density and the reliability of data reading, the development of ‘dry’ photopolymers that provide recording of superimposed three-dimensional phase holograms, and the designing of parallel optic input large-scale integration (LSI) for reading and logical processing of data arriving from the holographic memory.     

Implication of very wide fiber bandwidth for network architecture

The basic premise of this article is that at some point in the future all the transmission facilities of the public (telephone) network will be fiberoptic, i.e., end-to-end fiber connectivity will be provided to each subscriber. With the advent of coherent transmission systems the available bandwidth will become enormous, and thus the question we address is: given the availability of “infinite” bandwidth to every subscriber in the relatively near future, what does this imply for the network architecture? In particular, which switching technology is best suited to providing all foreseeable voice, data, and video services? Having discussed advantages and disadvantages of architectures based on different switching technologies, we conclude that an architecture based on circuit-switched, fixed-bandwidth channels for the transport of user information is the most appropriate for a network in which there are no constraints on the transmission bandwidth. The standard channel capacity should be determined by the service having the greatest bandwidth requirement.     

Reconfigurable silicon filter with continuous bandwidth tunability

We present the design and the fabrication of compact tunable silicon-on-insulator bandpass filters based on the integration of a Mach-Zehnder interferometer with ring resonators and activated via thermo-optic phase shifters. The proposed architecture provides wide filter bandwidth tunability from 10% to 90% of the free spectral range preserving the filter off-band rejection. Possible applications are channel subset selection in wavelength division multiplexing optical systems, adaptive filtering to signal bandwidth, and reconfigurable filters for gridless networking.     

忆阻器单阻态下的记忆电容行为及多态特性

采用供体-受体类型的共聚物构建了Al/共聚物/ITO结构的有机记忆器件,并对其电流-电压(I-V)和电容-电压(C-V)特性进行了研究.结果表明:器件不仅表现出明显的记忆电阻特征,而且在单个电阻状态下还存在记忆电容行为,使器件呈现出两种电阻状态和与之对应的四种电容状态,具有电阻和电容的双参量记忆能力.在此基础上对器件的电容开关行为进行了电压幅值的调制,使器件出现了更多的电容状态,为多级存储的实现提供了一条有效途径.最后通过引入分子内部极化算符,建立了记忆电阻和记忆电容的关联性,给出了描述器件双参量多状态特征的矩阵模型.     

Experimental Electrically Reconfigurable Time-Domain Spectral Amplitude Encoding/Decoding in an Optical Code Division Multiple Access System

Abstract

An electrically reconfigurable time-domain spectral amplitude encoding/decoding scheme is proposed herein. The setup is based on the concept of temporally pulse shaping dual to spatial arrangements. The transmitter is based on a short pulse source and uses two conjugate dispersive fiber gratings and an electro-optic intensity modulator placed in between. Proof of concept results are shown for an optical pulse train operating at 1.25 Gbps using codes from the Hadamard family with a length of eight chips. The system is electrically reconfigurable, compatible with fiber systems, and permits scalability in the size of the codes by modifying only the modulator velocity.     

Universal memory based on phase-change materials: From phase-change random access memory to optoelectronic hybrid storage

The era of information explosion is coming and information need to be continuously stored and randomly accessed over long-term periods, which constitute an insurmountable challenge for existing data centers. At present, computing devices use the von Neumann architecture with separate computing and memory units, which exposes the shortcomings of “memory bottleneck”. Nonvolatile memristor can realize data storage and in-memory computing at the same time and promises to overcome this bottleneck. Phase-change random access memory (PCRAM) is called one of the best solutions for next generation non-volatile memory. Due to its high speed, good data retention, high density, low power consumption, PCRAM has the broad commercial prospects in the in-memory computing application. In this review, the research progress of phase-change materials and device structures for PCRAM, as well as the most critical performances for a universal memory, such as speed, capacity, and power consumption, are reviewed. By comparing the advantages and disadvantages of phase-change optical disk and PCRAM, a new concept of optoelectronic hybrid storage based on phase-change material is proposed. Furthermore, its feasibility to replace existing memory technologies as a universal memory is also discussed as well.     

Proposal for loadable and erasable optical memory unit based on dual active microring optical integrators

A novel approach for loadable and erasable optical memory unit based on dual microring optical integrators is proposed and studied. The optical integrator, which can generate an optical step function for data storing, is synthesized using active media for loss compensation and a tunable phase shifter for data reading at any time. The input data into the memory is return-to-zero (RZ) signal, and the output data read from the memory is also RZ format with a narrower pulse width. An optical digital register based on the proposed optical memory unit is also investigated and simulated, which shows the potential for large scale data storage and serial-to-parallel data conversion. A great number of such memory units can be densely integrated on a photonic circuit for future large scale data storage and buffer.