1.5–2.5 nm RTP gate oxides: process feasibility, properties and limitations

To support the international roadmaps' requirements, semiconductor manufacturers must develop new processing technologies, both to shrink the dimensions and to improve the performances of devices. As a consequence, gate oxidation must advance to the 1.5–2.5 nm range over the coming years, to support the sub-0.18 μm technologies. We present here an overview of the more critical concern regarding this gate oxide downscaling. The limitations of rapid thermal processed (RTP) gate dielectric for oxide thickness <2 nm are discussed in terms of process feasibility, oxide thickness determination and maximum gate leakage current. As a result, we show that oxides as thin as 1.2 nm can be processed with control of the film uniformity (range within 0.06 nm). However, we also demonstrate that the exponential increase of the gate leakage current for oxides <2 nm does not allow integrating such thin dielectric layers in present metal oxide semiconductor (MOS) devices (oxide thickness limit around 2.3 nm).     

Extraction of the oxide thickness using a MOS structure quantum model for SiO2 oxide <5 nm thick films

In this paper, we present a full quantum model of metal oxide semiconductor capacitance based on a self-consistent resolution of Schrödinger and Poisson equations. The model is used in accumulation to extract the oxide thickness of N⁺ polycrystalline silicon–SiO₂–P silicon capacitors in the range 2–5 nm. The extraction results are in agreement with reference ellipsometric measurements to <±4%. We also show the necessity of a quantum computation of the gate capacitance for high substrate doping and low oxide thickness. The influence of the tunneling current is also discussed.     

Ultra-flat InP substrates produced using a chemo-mechanical polishing technique

One of the factors that may control the ultimate performance of semiconductor opto-electronic devices is that of substrate flatness. This communication discussed the main principles involved in improving the flatness of wafers polished using chemo-mechanical techniques. Results are presented for the polishing of InP using a solution of bromine in methanol. At low bromine concentrations ( <1%) the micro-roughness of the surface was reduced to <1 nm over a lateral spacing of 25 μm.     

Properties of ZrO2---Al2O3 composite powders prepared from Zr---Al metallo-organic compounds

Zr---Al metallo-organic compounds (zircoaluminates), having (CH₂)₄COOH, (CH₂)₁₂CH₃ and (CH₂)₂NH₂ as the organofunctional groups, were treated preliminary by (1) spray-drying, (2) gelation of addition of 10% NH₄OH aqueous solution followed by spray-drying and (3) rotary evaporation under a reduced pressure. After the treatment they were heated in air to prepare ZrO₂---Al₂O₃ composite powders. The IR and DTA profiles for the treated compounds indicated that the procedures modified the structures for the zircoaluminates. The stability of tetragonal ZrO₂ for the ZrO₂---Al₂O₃ composite powder were dependent on the modification in the structure for the zircoaluminates. Balloon shaped particles, 0.5–2 μm in diameter, were obtained through procedure (1) and spherical particles, 1–4 μm in diameter, through (2). Tetragonal ZrO₂ grains, 0.1–0.2 μm in diameter, were dispersed in the particles when heated at 1400°C.     

Effects of localized gate stack parasitic charge on current-voltage characteristics of double-gate MOSFETs with high-permittivity dielectrics and Ge-channel

In this paper we investigate the effects of localized gate stack parasitic charges on the current-voltage characteristics of double-gate (DG) MOSFET with metal/high-permittivity/Ge-channel using two-dimensional (2-D) numerical simulation. For this purpose a simulation code is developed, solving the Poisson equation on the entire device coupled self-consistently with the drift-diffusion transport equation. We show that the charges trapped at grain boundaries in the high-permittivity (high-κ) layer induce 2-D potential fluctuations in the structure, not only in the high-κ layer, but also in the underlying oxide and semiconductor regions. These potential fluctuations are shown to significantly degrade the subthreshold behavior of the drain current. The off-state drain current and the subthreshold slope increase with respect to the case where no charge is present in the gate stack. The influence of the location of the charged grain boundaries in the stack on the subthreshold parameters is also investigated using the 2-D numerical simulation code.     

Effects of rapid thermal treatments on the electrical properties of thin SiO2 gate oxide for DRAM p-channel MOS transistors

Silicon oxide has been grown by rapid thermal processing. The growth rate, in the range of very thin films (<10 nm), has been studied as a function of the oxidation temperature. Combined films composed by conventional thermal silicon oxide growth over SiO₂ passivation layer deposited by rapid thermal processing onto Si(1 0 0) substrates have been used as gate oxide of p-channel metal-oxide semiconductor (p-MOS) transistors of dynamic random access memory (DRAM). The effect of rapid thermal annealing treatments on these films has also been experimented. Improvements in the electrical performances of transistors have been observed.     

Simulation study of circuit performances of independent double-gate (IDG) MOSFETs with high-permittivity gate dielectrics

This study analyzes by 2-D numerical simulation the electrical performances of independent double-gate (IDG) MOSFET with high-permittivity (high-κ) dielectric gate stacks. We particularly address the operation of elementary devices as well as of the associated CMOS inverters, which are investigated in terms of static power dissipation and delay. We show that the introduction of a pure high-κ gate dielectric layer degrades the device immunity to short-channel effects and the power consumption of the CMOS inverter, but simultaneously improves the inverter speed, with respect to performances of a reference transistor with a SiO₂ gate oxide with the same equivalent oxide thickness. However, in real devices, the existence of a native oxide between the high-κ gate dielectric and the underlying semiconductor reduces parasitic electrostatic effects and sensibly improves inverter speed and power consumption. A detailed comparison between the operation of high-κ gate stack-based double-gate devices with independent and connected gates is also presented.     

Selectively embedded growth by chemical beam epitaxy for the fabrication of InGaAs/InP double-heterostructure lasers

In order to fabricate InGaAs/InP double-heterostructure (DH) lasers, a novel selectively embedded one-step growth by chemical beam epitaxy (CBE) was adopted. Before the selective CBE growth, 6–8 μm wide channels on an n-InP substrate were undercut by wet chemical etching through a 170 nm thick SiO₂ film mask. A 6 μm wide stripe-geometry DH laser structure with an active layer of 0.14 μm thickness was grown selectively with good planarity into the channels and operated by a pulse.     

Synthesis of window glazing coated with silica aerogel films via ambient drying

An ambient drying process (1 atm, 270 °C) has been developed in order to synthesize window glazing coated with silica aerogel films. The aerogel film could be manufactured by this process of wet gel films obtained via a dip-/spin-coating of the silica sol on a glass slide. Before drying, the isoproponol solvent in wet gels was exchanged with n-heptane to minimize the drying shrinkage. The thickness, refractive index, and porosity of silica films were 0.16–10 μm, 1.08–1.09, and 80–84%, respectively. The transmittance of window glazing was over 90% and we could predict that the optimal thermal conductivity (0.2 W/(m K)) of the window glazing would be obtained at the aerogel thickness of 100 μm (0.016 W/(m K)).     

Growth and spectral properties of Nd:LaVO4 crystal

This paper reports the growth and spectral properties of 3.5 at% Nd³⁺:LaVO₄ crystal with diameter of 20×15 mm² which has been grown by the Czochralski method. The spectral parameters were calculated based on Judd–Ofelt theory. The intensity parameters Ω_λ are: Ω₂=2.102×10⁻²⁰ cm², Ω₄=3.871×10⁻²⁰ cm², Ω₆=3.235×10⁻²⁰ cm². The radiative lifetime τ_r is 209 μs and calculated fluorescence branch ratios are: β₁(0.88μm)=45.2, β₂(1.06μm)=46.7, β₃(1.34μm)=8.1. The measured fluorescence lifetime τ_f is 137 μm and the quantum efficiency η is 65.6%. The absorption band at 808 nm wavelength has an FWHM of 20 nm. The absorption and emission cross sections are 3×10⁻²⁰ and 6.13×10⁻²⁰ cm², respectively.     

Silica aerogel films at ambient pressure

Silica films with refractive indices in the range of 1.006 – 1.036 (equivalent porosity 98.5–91%) have been prepared at ambient pressure by a process wherein organo-siloxane polymers are deposited on a silicon substrate by conventional dip-coating at 25°C and 0.85 bar (atmospheric pressure in Albuquerque) and heating to 450°C. The film thicknesses (from scanning electron microscopy) vary from 0.1 to 3.5 μm, depending upon the dip-coating rate (0.05 – 1.9 cm/s) and concentration of the sol. The process was optimized by varying the dilution, aging, organic modification, heat treatment and dip-coating conditions, allowing control of film porosity in the range 30–99%. Imaging ellipsometry has been used to study the evolution of film porosity and thickness in situ. It is observed that the high porosity in these films is mainly attributable to dilation or ‘springback’ of the film during the final stage of drying.     

InxGa1−xAs/GaAs quantum wire structures grown on GaAs (100) patterned substrates with [001] ridges

In_xGa_1−xAs/GaAs (x = 0.12-0.23) quantum well (QW) structures were grown by molecular beam epitaxy (MBE) on [001] ridges with various widths (1.1-12 μm) of patterned GaAs (100) substrate. The smallest lateral width of the InGaAs/GaAs quantum wire (QWR) structures was estimated to be about 0.1 μm by high-resolution scanning electron microscope (SEM). The In contents of the grown InGaAs/GaAs QWs on the ridges were studied as a function of ridge top width (ridge width of the MBE grown layer) by cathodoluminescence (CL) measurements at 78 K. Compared to the InGaAs QW grown on a flat substrate, the In content of the InGaAs/GaAs QW on the ridge increases from 0.22 to 0.23 when the ridge top width decreases to about 2.9 μm, but it decreases steeply from 0.23 down to 0.12 with a further decrease of the ridge width from 2.9 to 0.05 μm. A simulation of MBE growth of InGaAs on the [001] ridges shows that this reduced In content for narrow ridges is due to a large migration of Ga atoms to the (100) ridge top region from {110} side facets.     

Non-equilibrium gate tunneling current in ultra-thin (<2 nm) oxide MOS devices

The modeling of the electrical properties of ultra-thin (<2 nm thick) oxide metal–oxide–semiconductor (MOS) structures requires the self-consistent solution of the Schrödinger and the Poisson equations. To calculate the change density profile required by the Poisson equation, the occupancy of the quantum electronic states solution of the Schrödinger equation is a key issue. The most widely used approximation consists in assuming that the states that impinge from cathode and anode are occupied according to the Fermi–Dirac distribution with a quasi-Fermi (imref) level equal to that of the corresponding reservoir. The cathode and anode quasi-Fermi levels differ in the applied bias. In this work, we study the failure of this quasi-equilibrium approximation in the case of a MOS structure biased in accumulation. Our approach consists in considering the balance between inelastic scattering of electrons in the accumulation layer and the tunneling through the oxide. Using this procedure, we estimate that this quasi-equilibrium approximation fails for oxide thickness between 1 and 2 nm. Finally, we argued that kinetic treatments of transport are required for thinner oxides.     

InP/InGaAlAs distributed Bragg reflectors grown by low-pressure metal organic chemical vapor deposition

Long-wavelength vertical cavity surface emitting lasers (VCSELs) are considered the best candidate for the future low-cost reliable light sources in fiber communications. However, the absence of high refractive index contrast in InP-lattice-matched materials impeded the development of 1.3–1.5 μm VCSELs. Although wafer fusions provided the alternative approaches to integrate the InP-based gain materials with the GaAs/AlAs materials for their inherent high refractive index contrast, the monolithic InP-based lattice-matched distributed Bragg reflectors (DBRs) are still highly attractive and desirable. In this report, we demonstrate InP/InGaAlAs DBRs with larger refractive index contrast than InP/InGaAsP and InAlAs/InGaAlAs DBRs. The switching between InP and InGaAlAs layers and growth rate control have been done by careful growth interruption technique and accurate in situ optical monitoring in low-pressure metal organic chemical vapor deposition. A 35 pairs 1.55 μm centered InP/InGaAlAs DBRs has the stopband of more than 100 nm and the highest reflectivity of more than 99%. A VCSEL structure incorporating 35 pairs InP/InGaAlAs DBR as the bottom mirror combined with a 2λ thick periodic gain cavity and 10 pairs SiO₂/TiO₂ top dielectric mirrors was fabricated. The VCSELs lased at 1.56 μm by optical pumping at room temperature with the threshold pumping power of 30 mW.     

Microampere laser threshold at 80°C with InGaAs/GaAs/InGaP buried heterostructre strained quantum well lasers

An extremely low CW threshold current of 670 μA and a high slope efficiency of 0.14 W/A at a high junction temperature of 80°C were obtained with a 200 μm long Al-free InGaAs/GaAs/InGaP buried heterostructure (BH) quantum well laser grown by three-step metal organic vapor phase epitaxy (MOVPE). The maximum energy conversion efficiency of a 500 μm long laser was as high as 50% at a output power level of 1 mW. Regrowth conditions of InGaP layers were found to be crucial for planarizing the grown surface to realize the high performances.     

The role of Sb in the molecular beam epitaxy growth of 1.30–1.55 μm wavelength GaInNAs/GaAs quantum well with high indium content

Sb-assisted GaInNAs/GaAs quantum wells (QWs) with high (42.5%) indium content were investigated systematically. Transmission electron microscopy, reflection high-energy electron diffraction and photoluminescence (PL) measurements reveal that Sb acts as a surfactant to suppress three-dimensional growth. The improvement in the 1.55 μm range is much more apparent than that in the 1.3 μm range, which can be attributed to the difference in N composition. The PL intensity and the full-width at half maximum of the 1.55 μm single-QW were comparable with that of the 1.3 μm QWs.     

High-resolution XRD study of stress-modulated YBCO films with various thicknesses

High-quality epitaxial YBa₂Cu₃O_7−δ (YBCO) superconducting films with thicknesses between 0.2 and 2 μm were fabricated on (0 0 l) LaAlO₃ with direct-current sputtering method. The influence of film thickness on the structure and texture was investigated by X-ray diffraction conventional θ–2θ scan and high-resolution reciprocal space mapping (HR-RSM). The films grew with strictly c-axis epitaxial, and no a-axis-oriented growth was observed up to a thickness of 2 μm. Lattice parameters of the YBCO films with different thicknesses were extracted from symmetry and asymmetry HR-RSMs. The X-ray lattice parameter method was used to determine the residual stress in YBCO films by measuring the a-, b-, c-axis strains, respectively. The results showed that YBCO films within thinner than 1 μm were under compressive stress, which was relieved increasing of film thickness. However, beyond 1 μm in thickness, YBCO films exhibited a tensile stress. Based on the experimental analysis, the variety of residual stresses in the films is mainly attributed to oxygen vacancies with thickness of YBCO film increasing.     

Electrical properties of photoanodically generated thin oxide films on n-GaN

The characteristics of photoelectrochemically (PEC) generated gallium oxide films on n-GaN using an 0.002 M KOH electrolyte are described. The chemical composition of the resistive layers was analyzed by Auger electron spectroscopy. The DC and HF characteristics of Al/Ti/PEC-Ga₂O₃ (gallium sesquioxide)/GaN structures were studied with current–voltage and capacitance–voltage measurements, respectively. Under reverse bias we found extremely low leakage currents (<10⁻⁸ Acm⁻² at −15 V) and a very low interface state density; high-temperature operation (up to 166°C tested) motivates the integration of the described dielectric layer forming technique into GaN based device process schemes. Our method may also be employed as gate recess technology.     

Sol–gel synthesis and optical properties of size controlled Indium Arsenide nanocrystals embedded in silica glasses

III–V semiconductor Indium Arsenide (InAs) nanocrystals embedded in silica glasses was synthesized by combining the sol–gel process and heat treatment in H₂ gas. The size of InAs nanocrystals can be easily controlled via changing the In and As content in the starting materials and the heating temperature in a H₂ gas atmosphere. Absorption measurements indicate a blue shift in energy with a reduction on the In and As content in the SiO₂ gel glasses as a result of quantum confinement effects. A near-infrared photoluminescence with peak at 3.40 μm was observed at 6 K under 514.5 nm Ar⁺ laser excitation from InAs nanocrystals embedded in the silica gel glasses.     

Strain-compensated quantum cascade lasers operating at room temperature

Quantum cascade (QC) lasers based on strain-compensated In_xGa_(1−x)As/In_yAl_(1−y)As grown on InP substrate using molecular beam epitaxy is reported. The epitaxial quality is demonstrated by the abundant narrow satellite peaks of double-crystal X-ray diffraction and cross-section transmission electron microscopy of the QC laser wafer. Laser action in quasi-continuous wave operation is achieved at λ≈3.6–3.7μm at room temperature (34°C) for 20 μm×1.6 mm devices, with peak output powers of 10.6 mW and threshold current density of 2.7 kA/cm² at this temperature.