TI推出三款新型低功耗DSP与新型低功耗设计工具

德州仪器(TI)宣布推出三款新型低功耗DSP及新型eXpressDSP电源设计工具，帮助开发人员优化功耗设计、延长电池寿命，进一步降低便携式应用的成本。     

IC工具流支持新的电源标准

Cadence Design systems正在全力推动它有争议的公共电源促进(CPF)电源分析格式,而不管业内是否接受它.该公司本周将宣布,它的整个Ic设计流程将包括用此格式建立的新型低功耗设计技术.     

嵌入式系统的低功耗设计

本质上,低功耗设计并不需要魔法,但的确需要极大的努力关注和处理各种细节。     

Mentor Graphics公司Precision Synthesis工具全面支持QuickLogic超低功耗FPGA

近日，QuickLogic公司发布了来自其EDA领域合作伙伴Mentor Graphics公司所开发的、全面支持QuickLogic公司的微瓦级FPGA和可编程桥接产品的Precision Synthesis综合工具。Precision Synthesis综合工具集成了支持最小面积、功耗以及最佳性能等多项设计目标的优化策略的逻辑综合算法，为工程师在设计各种消费类电子产品时提供了强力支持。     

SOC技术及系统级低功耗设计

介绍了SOC设计中的IP核可复用技术、软硬件协同设计技术、SOC验证技术、可测性设计技术以及低功耗设计技术。对SOC低功耗设计中的瞬态功耗优化、平均功耗优化以及功耗的物理来源、电容充放电功耗、短路功耗、静电漏电功耗进行了分析。并对典型SOC设计中采取降低芯片和封装电容、降低电源电压,达到降低功耗的技术进行了研究。最后对系统级功耗设计中的电源系统低功耗设计、工作系统低功耗设计进行了探讨。     

新脚本工具在90nm工艺流程下实现低功耗设计提供对Synopsys和Cadence设计工具的全面支持

该脚本的新增功能包括自动生成物理设计流程脚本-这些脚本可以大幅降低功耗，自动输入用户定义的功耗结构以及支持串扰分析。通过利用Synopsys公司的Power Compiler的低功耗优化能力，同时在Xtensa LX内核和所有设计者自定义的扩展功能中自动的插入精细度时钟门控，可以降低动态功耗。     

EDA关注焦点:DFM工具及低功耗设计流程

DFM市场各显身手 随着半导体工艺向纳米时代的挺进，DFM工具也成为EDA行业中最为热门的话题。Cadence公司总裁兼CEO Michael J．Fister指出：“在90nm／65nm及今后的45nm设计中，DFM是影响良率的关键问题。目前，DFM工具占EDA整体市场份额的10％左右，今后将以更快的速度发展。”Mentor公司董事会主席兼CEO WaldenC．Rhines也表示，目前，DFM工具的年均增长率超过了15％，而整个EDA行业的年均增长率仅有2％。因此，DFM工具成为了各大EDA公司的必争之地。     

单片机应用系统的低功耗设计

介绍了一种单片机应用系统低功耗设计的方法，在野外动态测试技术中要求测试仪器长期工作，其能源必须由自身提供，即所谓的自容式，测试系统的低功耗设计是研制中面临的重要技术问题。     

使用ISE设计工具优化FPGA的功耗

Xilinx公司设计软件部 SubodhGupta博士,JasonAnderson博士 自从Xilinx公司推出FPGA二十多年来,研发工作大大提高了FPGA的速度和面积效率,缩小了FPGA与ASIC之间的差距,使FPGA成为实现数字电路的优选平台.今天,功耗日益成为FPGA供应商及其客户关注的问题.     

WEBENCH在线设计工具为电源设计工程师节省开发时间

密切关注电源设计工程师的需求,WEBENCH在线设计工具致力于可视化电源电路设计,并从尺寸、效率和BOM成本等方面优化设计,旨在满足设计要求的前提下缩短电源电路设计的时间。在进行电源电路设计时,设计人员首先要考虑的是输入电压、输出电流和电压范围。若是有多路输入多路负载,或者需要驱动FPGA/微处理器时,则要考虑多个输出需满足的精准电压、电流、纹     

Issues for low-power CAD tools: A system-level design study

A case study in low-power system-level design is presented. We detail the design of a low-power embedded system, a touchscreen interface device for a personal computer. This device is designed to operate on excess power provided by unused RS232 communication lines. We focus on the design and measurement procedures used to reduce the power requirements of this system to less than 50 mW. Additionally, we highlight opportunities to use system-level design and analysis tools for low-power design and the obstacles that prevented using such tools in this design.     

新型半静态低功耗D触发器设计

本文从简化触发器内部锁存器结构以降低功耗的要求出发，提出了一种新型的半静态D触发器设计。PSPICE模拟表明，新设计逻辑功能正确。与以往一些设计相比，新设计在功耗和速度上获得显著改进。     

EDA工具适应当今的FPGA设计

几年以前,高容量的现场可编程器件(FPGA)指 的是包含有5万个门电路,应用于逻辑结合比较紧密的 电路。但今天的FPGA已包含数百万个门电路,成为某 些增长最快的高科技市场的电子系统核心。摩尔定律在FPGA上呈现,包括门数与速率。高容量、高性能的FPGA已处在硅技术的前沿,甚至在某些场合替代了ASIC。     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

QuickLogic以μWattFPGA应对低功耗挑战

电子系统复杂性的不断提高导致其功耗要求相应提高,因此,设计人员必须寻找更好的途径去实现所需系统性能的同时又可有效地控制功耗.     

通信系统中超高效率Buck变换器设计考虑

目前,通信系统要求越来越快的处理速度.其内部专用集成芯片,处理器单元等电路所消耗的电流也越来越大,同时,为了减小系统的体积和尺寸,内部的低压大电流的DC/DC变换器不断向高频、高密度方向发展.频率的提高带来系统变换效率的降低,另外,由于世界范围能源危机和环境污染提出了对节能减排的要求,因此,基于高频的变换器必须采用新型的器件,从而可以保证系统既工作在高频状态下,实现小尺寸,小体积,又整体的提高系统的效率,实现节能减排的目的.效率的整体提高进一步降低了电源系统的发热量,提高系统的可靠性.通信系统内部的系统板上使用了大量的Buck变换器,本文将针对这种变换器进行详细的讨论.     

Segmented bus design for low-power systems

This paper proposes a bus-segmentation method that efficiently reduces the switched capacitance on the bus. The power consumed by the bus can, therefore, be substantially reduced. The basic idea of bus segmentation is to partition the bus into several bus segments separated by pass transistors. Highly communicating devices are located to adjacent bus segments, thus, most data communication can be achieved by switching a small portion of the bus segments. As a result, power consumption and critical path delay are both reduced. Experimental results obtained by simulating a delay model and a power model demonstrate that the proposed segmented bus system reduces bus power by about 60%-70% and improves critical bus delay by about 10%-30%     

Considering the alternatives in low-power design

The authors discuss employing alternative number systems to reduce power dissipation in portable devices and high-performance systems. They focus on two alternative number systems that are quite different from the conventional linear number representations, namely the logarithmic number system (LNS) and the residue number system (RNS). Both have recently attracted the interest of researchers for their low-power properties. The authors address aspects of the conventional arithmetic representations, the impact of logarithmic arithmetic on power dissipation, and discuss the low-power aspects of residue arithmetic     

Process-insensitive low-power design of switched-capacitor integrators

A generalized analytical technique is developed to design power optimized switched-capacitor integrators taking process variations into account. It is shown that the performance of a robustly designed power optimum switched-capacitor integrator is a monotonic function of the slew rate and the transconductance of the amplifier. The framework provides an analytical solution for fabrication foundry independent analog design and therefore eliminates the need for Monte Carlo simulations to estimate the effect of the worst-case performance variations. With this analytical approach, it is possible to migrate the design to technologies with smaller feature sizes while obtaining monotonic improvement in the performance. The validity of the proposed analytical model for the design of robust switched-capacitor integrators is demonstrated through transistor-level SPICE simulations using BSIM3v3 models.     

支持智能能源管理让ZigBee更环保

自2004年发布第一个规范以来,ZigBee标准现在已经发展成熟到能够获得全世界认可的地步,并开始在市场上发挥举足轻重的作用.ZigBee提供了一个高性价比、基于多种标准的无线网络解决方案,该方案支持以低数据速率,低功耗网络通信为重点的技术.