Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.     

Study on the recovery of NBTI of ultra-deep sub-micro MOSFETs

Taking the actual operating condition of complementary metal oxide semiconductor (CMOS) circuit into account, conventional direct current (DC) stress study on negative bias temperature instability (NBTI) neglects the detrapping of oxide positive charges and the recovery of interface states under the `low' state of p-channel metal oxide semiconductor field effect transistors (MOSFETs) inverter operation. In this paper we have studied the degradation and recovery of NBTI under alternating stress, and presented a possible recovery mechanism. The three stages of recovery mechanism under positive bias are fast recovery, slow recovery and recovery saturation.     

Degradation characteristics and mechanism of PMOSFETs under NBT--PBT--NBT stress

Degradation characteristics of PMOSFETs under negative bias temperature--positive bias temperature--negative bias temperature (NBT--PBT--NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.     

High-field-induced electron detrapping in An AlGaN/GaN high electron mobility transistor

A step stress test is carried out to study the reliability characteristics of an AlGaN/GaN high electron mobility transistor(HEMT).An anomalous critical drain-to-gate voltage with a negative temperature coefficient is observed in the stress sequence,beyond which the HEMT device starts to recover from degradation induced by early lower voltage stress.While the performance degradation featuring the drain current slump stems from electron trapping in the surface or bulk states during low-to-medium bias stress,the recovery is attributed to high field induced electron detrapping.The carrier detrapping mechanism could be helpful for lessening the trapping-related performance degradation of a GaN-based HEMT.     

Influence of white light illumination on the performance of a-IGZO thin film transistor under positive gate-bias stress

The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed.     

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress (NBS) is observed for amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs), which can recover in a short time. After comparing with the degradation phenomena under negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias illumination stress (PBIS), degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies ($V_{\mathrm{o}}^{+}$) in addition to the commonly reported doubly charged oxygen vacancies ($V_{\mathrm{o}}^{2+}$). Furthermore, the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of $V_{\mathrm{o}}^{+}$ under positive gate bias. The proposed degradation mechanisms are verified by TCAD simulation.     

Effect of substrate bias on negative bias temperature instability of ultra-deep sub-micro p-channel metal--oxide--semiconductor field-effect transistors

The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electron--hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.     

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium–gallium–zinc oxide thin film transistor, which adopts an elevated-metal metal–oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction.The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the backchannel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device(L = 2 μm). It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

Kink effect in AlGaN/GaN high electron mobility transistors by electrical stress

The kink effect is studied in an AlGaN/GaN high electron mobility transistor by measuring DC performance during fresh, short-term stress and recovery cycle with negligible degradation. Vdg plays an assistant role in detrapping electrons and short-term stress results in no creation of new category traps but an increase in number of active traps. A possible mechanism is proposed that electrical stress supplies traps with the electric field for activation and when device is under test field-assisted hot-electrons result in electrons detrapping from traps, thus deteriorating the kink effect. In addition, experiments show that the impact ionization is at a relatively low level, which is not the dominant mechanism compared with trapping effect. We analyse the complicated link between the kink effect and stress bias through groups of electrical stress states: Vds = 0-state, off-state, on-state (on-state with low voltage, high-power state, high field state). Finlly, a conclusion is drawn that electric field brings about more severe kink effect than hot electrons. With the assistance of electric field, hot electrons tend to be possible to modulate the charges in deep-level trap.     

Effects of DC and AC stress on the VT shift of AlGaN/GaN MIS-HEMTs

AlGaN/GaN MIS-HEMTs with adjusted V_T were fabricated using a recess gate to investigate the effect on actual operation when the polarity of the gate voltage is opposite in the on- and off-state. The direction and time exponents of V_T shift depend on the polarity of the gate bias stress. Electrons detrapping from the Al₂O₃/AlGaN interface trap site to AlGaN under negative gate bias stress has to overcome the energy barrier, resulting in a higher temperature dependence. In addition, the unaffected g_m and SS show that the degradation occurred primarily at the Al₂O₃/AlGaN interface rather than channel or mobility degradation. For unipolar and bipolar AC stresses, the time exponent of the V_T shift during stress time has two values, and a relatively low value during relaxation after bipolar AC stress. These results may be due to the further degradation by V_min at the broader energy levels of the Al₂O₃/AlGaN interface.     

Hot carrier injection degradation under dynamic stress

In this paper,we have studied hot carrier injection(HCI) under alternant stress.Under different stress modes,different degradations are obtained from the experiment results.The different alternate stresses can reduce or enhance the HC effect,which mainly depends on the latter condition of the stress cycle.In the stress mode A(DC stress with electron injection),the degradation keeps increasing.In the stress modes B(DC stress and then stress with the smallest gate injection) and C(DC stress and then stress with hole injection under V g = 0 V and V d = 1.8 V),recovery appears in the second stress period.And in the stress mode D(DC stress and then stress with hole injection under V g = 1.8 V and V d = 1.8 V),as the traps filled in by holes can be smaller or greater than the generated interface states,the continued degradation or recovery in different stress periods can be obtained.     

Long-term stability of InP MIS devices

Room-temperature bias stress measurements were performed on n-type InP MIS capacitors. A wide range of interface passivation processes and gate dielectrics was investigated. A generally observed behaviour under positive bias stress is a slow trapping - fast detrapping consistent with a trap distribution in the interfacial layer above the conduction band edge of InP. Large variations both in the magnitude and in the time dependence of the flat-band voltage shift ΔV_FB are observed. We discuss these drift behaviours in terms of interface traps - rather than bulk dielectric traps - in relation with the physico-chemical properties of the interface. It is shown that devices based on InP treated by annealing under arsenic pressure and controlled oxidation exhibit a very good stability. For any passivation procedure, the drift is strongly diminished if the device is stressed with AC voltage compared to DC voltage.     

Evaluation of negative bias temperature instability in ultra-thin gate oxide pMOSFETs using a new on-line PDO method

A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by I_D-V_D characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous on-the-fly method. It is found that both reaction--diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90\du\ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction--diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction--diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

Time-dependent degradation of threshold voltage in AlGaN/GaN high electron mobility transistors

This paper gives a detailed analysis of the time-dependent degradation of the threshold voltage in AlGaN/GaN high electron mobility transistors(HEMTs) submitted to off-state stress. The threshold voltage shows a positive shift in the early stress, then turns to a negative shift. The negative shift of the threshold voltage seems to have a long recovery time. A model related with the balance of electron trapping and detrapping induced by shallow donors and deep acceptors is proposed to explain this degradation mode.     

超深亚微米PMOS器件的NBTI退化机理

对超深亚微米PMOS器件的负栅压温度不稳定性(NBTI)退化机理进行了研究.主要集中在对器件施加NBT和随后的PBT应力后器件阈值电压的漂移上.实验证明反型沟道中空穴在栅氧中的俘获以及氢分子在栅氧中的扩散是引起NBTI退化的主要原因.当应力条件变为PBT时，陷落的空穴可以快速退陷，但只有部分氢分子可以扩散回栅氧与衬底界面钝化硅悬挂键，这就导致了PBT条件下阈值电压只能部分恢复. 关键词： 超深亚微米PMOS器件 负偏压温度不稳定性 界面陷阱 氢气     

MOS结构中薄栅氧化层高场退火效应的研究

深入研究了MOS结构中薄栅氧化层在高电场下的退火效应,对氧化层陷阱电荷的退陷阱机理进行了深入探讨.通过实验和模拟对氧化层陷阱电荷的退陷阱机理和生长机理进行了比较,给出了满意的物理解释.负栅压退火和正栅压退火的比较表明负栅压退火更为有效     

NBT导致的深亚微米PMOS器件退化与物理机理

研究了深亚微米PMOS器件在负偏压温度(negative bias temperature, NBT) 应力前后的电流电压特性随应力时间的退化，重点分析了NBT应力对PMOS器件阈值电压漂移的影响，通过实验证明了在栅氧化层和衬底界面附近的电化学反应和栅氧化层内与氢相关的元素的扩散，是PMOS器件中NBT效应产生的主要原因.指出NBT导致的PMOS器件退化依赖于反应机理和扩散机理两种机理的平衡. 关键词： 深亚微米PMOS器件 负偏压温度不稳定性 界面态 氧化层固定正电荷     

Energy distribution extraction of negative charges responsible for positive bias temperature instability

A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability(PBTI) stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 e V above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.