不恢复余数法的等效变形—阵列除法器的数学分析(Ⅱ)

运算器对于CPU的性能有重要影响,除法器是运算器的一个重要组件.除法器电路常用不恢复余数法,但声称采用了不恢复余数法的各种电路采用的算法却有明显区别.及其前导文试图对不恢复余数法和不恢复余数阵列除法器电路进行分析.前导给出了不恢复余数法的一种初始形式,将给出初始形式的等效变形并展示阵列除法器电路是这种等效算法的硬件实现.     

计算一类数字变换的收缩阵列

本文以DFT的收缩（Systolic）阵列结构为基础，给出了一类数字变换的收缩阵列，这些变换包括离散富里叶变换，离散余弦变换，离散正弦变换，离散Hartley变换，数论变换和多项式变换．     

FPGA Realization of Fractional Order Neuron

In this paper fractional Hindmarsh Rose (HR) neuron, which mimics several behaviors of a real biological neuron is implemented on field programmable gate array (FPGA). The results show several differences in the dynamic characteristics of integer and fractional order Hindmarsh Rose neuron models. The integer order model shows only one type of firing characteristics when the parameters of model remains same. The fractional order model depicts several dynamical behaviors even for the same parameters as the order of the fractional operator is varied. The firing frequency increases when the order of the fractional operator decreases. The fractional order is therefore key in determining the firing characteristics of biological neurons. To implement this neuron model first the digital realization of different fractional operator approximations are obtained, then the fractional integrator is used to obtain the low power and low cost hardware realization of fractional HR neuron. The fractional neuron model has been implemented on a low voltage and low power circuit and then compared with its integer counter part. The hardware is used to demonstrate the different dynamical behaviors of fractional HR neuron for different type of approximations obtained for fractional operator in this paper. A coupled network of fractional order HR neurons is also implemented. The results also show that synchronization between neurons increases as long as coupling factor keeps on increasing.     

An efficient serial distributed arithmetic algorithm for FPGA implementation of digital up conversion

This article deals with a computationally efficient serial distributed arithmetic algorithm producing a device efficient field programmable gate array implementation. The proposed algorithm takes half the computations time as compared to the conventional symmetric algorithms. The algorithm is analyzed for a direct conversion transmitter of ionospheric radar. Matching and buffering criterion are used to reduce the arithmetic process. The algorithm can be extended to applications with similar characteristics, particularly for System On Chip (SOC) techniques. © 2005 Wiley Periodicals, Inc. Complexity 11: 24–29, 2005     

Synthesis of a unidirectional systolic array for matrix–vector multiplication

In this paper we present a procedure, based on data dependencies and space–time transformations of index space, to design a unidirectional linear systolic array (ULSA) for computing a matrix–vector product. The obtained array is optimal with respect to the number of processing elements (PEs) for a given problem size. The execution time of the array is the minimal possible for that number of PEs. To achieve this, we first derive an appropriate systolic algorithm for ULSA synthesis. In order to design a ULSA with the optimal number of PEs we then perform an accommodation of the index space to the projection direction vector. The performance of the synthesized array is discussed and compared with the bidirectional linear SA. Finally, we demonstrate how this array can be used to compute the correlation of two given sequences.     

基于声矢量水听器阵列误差的自校正算法

对声矢量水听器阵列的各类误差进行了分类,推导了各类误差对阵列信号模型的影响因子,通过Monte Carlo实验分析对比了各类误差对阵列DOA估计性能的影响,然后将方向性误差和位置误差归结为幅度误差和相位误差,在传统声压阵列误差校正模型和算法的基础上,得到矢量阵列误差自校正的优化模型及自校正算法,最后,通过仿真实验和外场实验的数据处理表明,自校正算法具有良好的参数估计性能,具有一定的工程实用性.     

Riordan 矩阵在广义 Motzkin 路计数中的应用

用Riordan矩阵的方法研究了具有4种步型的加权格路(广义Motzkin路)的计数问题,引入了一类新的计数矩阵,即广义Motzkin矩阵.同时给出了这类矩阵的Riordan表示,也得到了广义Motzkin路的计数公式.Catalan矩阵,Schrder矩阵和Motzkin矩阵都是广义Motzkin矩阵的特殊情形.     

Four Easy Ways to a Faster FFT

The Fast Fourier Transform (FFT) was named one of the Top Ten algorithms of the 20th century , and continues to be a focus of current research. A problem with currently used FFT packages is that they require large, finely tuned, machine specific libraries, produced by highly skilled software developers. Therefore, these packages fail to perform well across a variety of architectures. Furthermore, many need to run repeated experiments in order to re-program their code to its optimal performance based on a given machine's underlying hardware. Finally, it is difficult to know which radix to use given a particular vector size and machine configuration. We propose the use of monolithic array analysis as a way to remove the constraints imposed on performance by a machine's underlying hardware, by pre-optimizing array access patterns. In doing this we arrive at a single optimized program. We have achieved up to a 99.6% increase in performance, and the ability to run vectors up to 8388608 elements larger, on our experimental platforms. Preliminary experiments indicate different radices perform better relative to a machine's underlying architecture.     

Entorno geométrico eficiente para el modelado de imágenes en 3D

The objective of this paper is exploring implementation of a realistic images reconstruction 3D using geometric algebra (GA). We illustrate the suitability of GA for representing structures and developing algorithms in computer graphics, especially for engineering applications as 3D images modeling. A first consequence is to propose an efficient framework model to be implemented in hardware programmable. The obtained results showed that using GA, the computations are less complex and shows as simple computations geometrical operations. The obtained model to hardware can be implemented as a next step in 3D image reconstruction. We also include the potential of GA for optimizations and highly efficient implementations.     

A graph theoretical approach for the yield enhancement of reconfigurable VLSI/WSI arrays

In this paper, we consider the yield enhancement of programmable structures by logical restructuring of the circuit placement. In this approach, an initial placement of a circuit on the array is first obtained by simulated annealing on a defect-free array. To implement the circuit on a defective array, the initial placement is reconfigured so that only the defect-free portion of the array is used. Customizing a given initial placement for each defective chip by logical restructuring, if done very fast, would be a cost effective method for yield enhancement. We describe a formulation of the circuit reconfiguration problem in terms of graphs and pebbles, wherein each processing element (PE) of the array is represented by a vertex which is classified as either defective or nondefective, depending upon whether the PE that it represents is defective or nondefective. Vertices representing PEs that are physically adjacent are connected by an edge, whose length is a measure of the proximity of the PEs. The logic elements of a circuit are represented by weighted pebbles. The initial placement of the circuit on the array corresponds to an initial placement of the pebbles on the vertices of the graph, with at most one pebble per vertex. The problem is to successively shift these pebbles along paths in the graph, such that after reconfiguration no pebble is located on a defective vertex, and an associated cost function is minimized. We describe four cost measures using weighted displacement and weighted shift of the pebbles. After presenting exact algorithms for some special cases of the problem, we prove the NP-completeness of the general cases of the corresponding decision problems.     

WIDE SENSE STABILITY OF COMPLEX SYSTEMS OF DIFFERENTIAL EQUATIONS OF ARBITRARY DIMENSION

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Products of mixed covering arrays of strength two

A covering array CA(N;t,k, v is an N × k array such that every N × t subarray contains all t‐tuples from v symbols at least once, where t is the strength of the array. Covering arrays are used to generate software test suites to cover all t‐sets of component interactions. The particular case when t = 2 (pairwise coverage) has been extensively studied, both to develop combinatorial constructions and to provide effective algorithmic search techniques. In this paper, a simple “cut‐and‐paste” construction is extended to covering arrays in which different columns (factors) admit different numbers of symbols (values); in the process an improved recursive construction for covering arrays with t = 2 is derived. © 2005 Wiley Periodicals, Inc. J Combin Designs 14: 124–138, 2006     

Half Inverse Riordan Arrays and Their Related Vertical Recurrence Relation

We discuss two different procedures to study the half Riordan arrays and their inverses. One of the procedures shows that every Riordan array is the half Riordan array of a unique Riordan array. It is well known that every Riordan array has its half Riordan array. Therefore, this paper answers the converse question: Is every Riordan array the half Riordan array of some Riordan arrays? In addition, this paper shows that the vertical recurrence relation of the column entries of the half Riordan array is equivalent to the horizontal recurrence relation of the original Riordan array''s row entries.     

EOL and ETOL array languages

In this paper we study the families of ETOL and EOL array languages. Standard forms for ETOL and EOL array systems are defined and closure properties of the families are studied. Relations of these families with other developmental array languages and other array languages are studied.     

Covering arrays of higher strength from permutation vectors

A covering array CA(N;t,k,v) is an N × k array such that every N × t sub‐array contains all t‐tuples from v symbols at least once, where t is the strength of the array. Covering arrays are used to generate software test suites to cover all t‐sets of component interactions. We introduce a combinatorial technique for their construction, focussing on covering arrays of strength 3 and 4. With a computer search, covering arrays with improved parameters have been found. © 2005 Wiley Periodicals, Inc. J Combin Designs 14: 202–213, 2006     

Lattice embeddings and array noncomputable degrees

We focus on a particular class of computably enumerable (c. e.) degrees, the array noncomputable degrees defined by Downey, Jockusch, and Stob, to answer questions related to lattice embeddings and definability in the partial ordering (??, ≤) of c. e. degrees under Turing reducibility. We demonstrate that the latticeM₅ cannot be embedded into the c. e. degrees below every array noncomputable degree, or even below every nonlow array noncomputable degree. As Downey and Shore have proved that M₅ can be embedded below every nonlow₂ degree, our result is the best possible in terms of array noncomputable degrees and jump classes. Further, this result shows that the array noncomputable degrees are definably different from the nonlow₂ degrees. We note also that there are embeddings of M₅ in which all five degrees are array noncomputable, and in which the bottom degree is the computable degree 0 but the other four are array noncomputable. (© 2004 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Parallel factorization of banded linear matrices using a systolic array processor

A parallel algorithm for calculating theQR factorization of a banded system of linear equations using a systolic array processor is presented and an application to spline fitting is given. The major advantage of the method is that the size of the processor array is fixed by the size of the bandwidth of the system to be solved. This allows the factorization of large systems using small systolic arrays. The cost of the method, in terms of storage and time, is optimal.     

Suffix array and Lyndon factorization of a text

The main goal of this paper is to highlight the relationship between the suffix array of a text and its Lyndon factorization. It is proved in [15] that one can obtain the Lyndon factorization of a text from its suffix array. Conversely, here we show a new method for constructing the suffix array of a text that takes advantage of its Lyndon factorization. The surprising consequence of our results is that, in order to construct the suffix array, the local suffixes inside each Lyndon factor can be separately processed, allowing different implementative scenarios, such as online, external and internal memory, or parallel implementations. Based on our results, the algorithm that we propose sorts the suffixes by starting from the leftmost Lyndon factors, even if the whole text or the complete Lyndon factorization are not yet available.     

A construction of maximal linearly independent array

Let M be a subset of r-dimensional vector space Vτ （F2） over a finite field F2, consisting of n nonzero vectors, such that every t vectors of M are linearly independent over F2. Then M is called （n, t）-linearly independent array of length n over Vτ（F2）. The （n, t）-linearly independent array M that has the maximal number of elements is called the maximal （r, t）-linearly independent array, and the maximal number is denoted by M（r, t）. It is an interesting combinatorial structure, which has many applications in cryptography and coding theory. It can be used to construct orthogonal arrays, strong partial balanced designs. It can also be used to design good linear codes, In this paper, we construct a class of maximal （r, t）-linearly independent arrays of length r ＋ 2, and provide some enumerator theorems.     

Risk analysis techniques and their application to software development

The past decade has seen a dramatic change in the emphasis of software to hardware. Whereas a project may have comprised 80% hardware and 20% software, the reverse is now generally more realistic. This has resulted in a great deal of interest focusing around the areas of quality metrics and reliability growth applied to the software lifecycle. Risk analysis has to date seen many applications in the assessment of hardware but little in the software area. This paper reviews the risk analysis techniques that have been developed in a range of industries. Progress in this area has been most apparent in the chemical and nuclear power industries where probabilistic risk assessment has been used to estimate the total risk associated with the whole plant. A discussion of the appropriateness of the techniques to software safety assessment is included together with an outline of the methods currently being used to detect software faults. Suggestions are made for a new methodology in analysing software safety.