Ambipolar organic field-effect transistors on unconventional substrates

In this paper we report on the realization of flexible all-organic ambipolar field-effect transistors (FETs) realized on unconventional substrates, such as plastic films and textile yarns. A double layer pentacene-C₆₀ heterojunction was used as the semiconductor layer. The contacts were made with poly(ethylenedioxythiophene)/poly(styrenesulfonate) (PEDOT:PSS) and patterned by means of soft lithography microcontact printing (μCP). Very interestingly growing C₆₀ on a predeposited pentacene buffer layer leads to a clear improvement in the morphology and crystallinity of the film so it obtains n-type conduction despite the very high electron injection barrier at the interface between PEDOT:PSS and C₆₀. As a result, it was possible to obtain all-organic ambipolar FETs and to optimize their electrical properties by tuning the thicknesses of the two employed active layers. Moreover, it will be shown that modifying the triple interface between dielectric/semiconductor/electrodes is a crucial point for optimizing and balancing injection and transport of both kinds of charge carriers. In particular, we demonstrate that using a middle contact configuration in which source and drain electrodes are sandwiched between pentacene and C₆₀ layers allows significantly improving the electrical performance in planar ambipolar devices. These findings are very important because they pave the way for the realization of low-cost, fully flexible and stretchable organic complementary circuits for smart wearable and textile electronics applications.     

Amorphous silicon logic integrated circuits

Amorphous silicon thin-film integrated circuits, with between 4 and 18 transistor functions per chip, have been fabricated on glass substrates. The amorphous silicon and the dielectric layers are deposited by rf glow discharge. The circuits have been designed to realize basic logic functions such as inverters, NAND and NOR gates, and addressable memory cells. For the first time, an amorphous silicon flip flop requiring a supply voltage of only 4.5 V has been manufactured. The logic voltage levels of the flip flop are compatible with standard bipolar TTL circuits. Measurements on an inverter chain show a typical propagation delay time of 70 s and a power-delay-time product of 65 pJ. All of the circuits use n-channel enhancement type load transistors instead of integrated ohmic load resistors. The channel length of the driver transistors is 15 m with a gate source/drain overlap of 7.5 m. Experimental geometry ratios range from =2.25 to =21. Generally, the driver transistors exhibit on/off ratios greater than 10⁶ for supply voltages smaller than 5 V. At these voltages the measured on-currents per unit channel width are in the order of 5...10nA/m.The influence of the geometry ratio on static inverter characteristic and switching speed is discussed by means of a simple model. Two different manufacturing schemes for the fabrication of the integrated circuits are outlined. Mask layouts and experimental transfer characteristics of several integrated circuits are presented.     

Laser forward transfer of silver electrodes for organic thin-film transistors

Organic thin-film transistors (OTFTs) with top- and bottom-contact configurations were fabricated using silver nano-inks printed by laser forward transfer for the gate and source/drain electrodes with pentacene and poly-4-vinylphenol as the organic semiconductor and dielectric layers, respectively. The volume of the laser-printed Ag pixels was typically in the subpicoliter (0.2–0.4 pl) range. The top-contact OTFTs resulted in lower contact resistance compared to those obtained from the bottom-contact OTFTs, and showed improved overall device performance. The top-contact OTFTs exhibited field-effect mobilities of ∼0.16 cm² V⁻¹ s⁻¹ and on/off current ratios of ∼10⁵.     

Influence of self-assembled monolayer chain length on modified gate dielectric pentacene thin-film transistors

Self-assembled monolayers are widely used to modify the gate dielectric/semiconductor interface in organic thin-film transistors. By modifying the interaction between the molecular semiconductor and the substrate, thin-film ordering and the electronic properties of the semiconducting channel can be controlled. The modified semiconductor/dielectric properties result in macroscopically observed changes in the charge-carrier mobilities, threshold voltages, subthreshold swing and transfer characteristic hysteresis. The latter two are determined by the density of charge-trapping states at the interface. Here, we investigate the influence of the thickness of the self-assembled monolayer, via the alkyl chain length in n-alkyl phosphonic acid-based monolayers on SiO₂, on the electronic properties of pentacene-based organic thin-film transistors. Rather than a monotonic increase or decrease in performance with increasing chain length, we have found that the optimum performance occurs with chains of 8–10 carbon atoms. Atomic force microscopy shows a correlation between pentacene crystalline grain size and transistor performance.     

A DC current–voltage model for organic thin film transistor for circuit design

Organic integrated circuits based on organic thin film transistors (OTFT) are gaining more and more attention nowadays, the availability of accurate spice-like device model for OTFTs suitable for Electronic design automation (EDA) applications is particularly attractive. In this paper, we demonstrate the applicability of the accurate direct-current (DC) model for OTFTs suitable for EDA, the parameters in the unified model all can be extracted in a simple and direct way from the experimental measurements. Two types of top source and drain contact (TC) pentacene TFTs with different gate dielectrics are researched on, simulation results based Simulation Program with Integrated Circuit Emphasis (SPICE) are obtained with this model and parameters extracted, which show a very good agreement with measured curves in both transfer and output characteristics, so the DC model and the extracted parameters are verified.     

Extrinsic limiting factors of carrier transport in organic field-effect transistors

Extrinsic factors to disturb the carrier transport in pentacene field-effect transistors (FETs), as a representative of the high-mobility organic FETs (OFETs), have been comprehensively analyzed by using atomic-force-microscope potentiometry (AFMP), microscopic four-point-probe field-effect transistor (MFPP-FET) measurement, and other techniques. In the first part, by mainly using AFMP as a powerful tool to reveal the potential distribution in working OFETs, we show how and how much the formation of source/drain electrodes influences the apparent field-effect mobility both for top- and bottom-contact configurations. In the second part, we show the influence of irregular grain structures and regular grain boundaries. The films grown both at very low and high temperature ranges contain distinctive insulating parts, which make the apparent mobility very low. Within the moderate growth temperature range, the intrinsic field-effect mobility obtained by MFPP-FET measurement is proportional to the average grain size. This behavior is well explained by the polycrystalline model with the diffusion theory. According to the observations in this work, it is obvious that these extrinsic limiting factors must be carefully excluded to discuss the intrinsic mechanism of the carrier transport in OFETs.     

Continuous tuning of the threshold voltage of organic thin-film transistors by a chemically reactive interfacial layer

For the design and manufacture of complex integrated circuits, control over the threshold voltage of the transistors is essential. In the present contribution, we present a non-invasive method to tune the threshold voltage of organic thin-film transistors after device assembly over a wide range without any significant degradation of the device characteristics. This is realized by incorporating a thin, chemically reactive siloxane layer bonded to the gate oxide. This results in threshold voltages of around 70 V in the as-prepared devices. By exposing a transistor modified in this way to ammonia at different concentrations, the threshold voltage can be tuned in steps of only a few volts. This treatment affects only the charge density at the semiconductor–dielectric interface, leaving the overall shape of the transistor characteristics and the charge-carrier mobility largely unaltered.     

Laser printing of polythiophene for organic electronics

We report on the development of hybrid organic/inorganic thin-film transistors using regioregular poly-3-hexylthiophene (P3HT) semiconductor material deposited by means of the solid-phase Laser Induced Forward Transfer (LIFT) technique. P3HT pixels were LIFT-printed onto Au/Ti source and drain electrodes formed on silicon dioxide/p⁺-type Si substrate. Deposition of the P3HT pixels was investigated as a function of the laser fluence using donor substrates with and without a dynamic release layer. Device electrical characterization reveals efficient field-effect action of the bottom gate on the organic channel. The transfer I_DS-V_GS characteristics exhibit well-defined sub-threshold, linear and saturation regimes designating LIFT as a promising technique for hybrid organic/inorganic transistor technology.     

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×10¹³ el/cm², a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×10¹⁴ el/cm² was observed.     

Amorphous IZO TTFTs with saturation mobilities exceeding 100 cm2/Vs

In this paper we demonstrate the use of amorphous binary In₂O₃–ZnO oxides simultaneously as active channel layer and as source/drain regions in transparent thin film transistor (TTFT), processed at room temperature by rf sputtering. The TTFTs operate in the enhancement mode and their performances are thickness dependent. The best TTFTs exhibit saturation mobilities higher than 10² cm²/Vs, threshold voltages lower than 6 V, gate voltage swing of 0.8 V/dec and an on/off current ratio of 10⁷. This mobility is at least two orders of magnitude higher than that of conventional amorphous silicon TFTs and comparable to or even better than other polycrystalline semiconductors. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Subthreshold regime in rubrene single-crystal organic transistors

Organic field-effect transistors were fabricated with vapor-grown rubrene single crystals in a staggered top-contact configuration. The devices were electrically characterized by measuring the transfer curves at low drain voltage. In parallel to these measurements, a model is developed to account for the subthreshold regime of the transistors. The model is based on the multiple trapping and thermal release concept, which assumes that charge transport is limited by a single level of shallow traps located close to the transport band edge. It is shown that the threshold voltage no longer establishes at the transition between the depletion and accumulation regimes. Instead, the threshold corresponds to the point at which traps are filled. This results in a subthreshold current that varies linearly with gate voltage. Moreover, the subthreshold current at low drain voltages increases with drain voltage. These finding are in good agreement with the experimental data.     

Enhanced electrical properties of pentacene-based organic thin-film transistors by modifying the gate insulator surface

A reliable surface treatment for the pentacene/gate dielectric interface was developed to enhance the electrical transport properties of organic thin-film transistors (OTFTs). Plasma-polymerized fluorocarbon (CFx) film was deposited onto the SiO₂ gate dielectric prior to pentacene deposition, resulting in a dramatic increase of the field-effect mobility from 0.015 cm²/(V s) to 0.22 cm²/(V s), and a threshold voltage reduction from −14.0 V to −9.9 V. The observed carrier mobility increase by a factor of 10 in the resulting OTFTs is associated with various growth behaviors of polycrystalline pentacene thin films on different substrates, where a pronounced morphological change occurs in the first few molecular layers but the similar morphologies in the upper layers. The accompanying threshold voltage variation suggests that hole accumulation in the conduction channel-induced weak charge transfer between pentacene and CFx.     

Application of amorphous silicon field effect transistors in addressable liquid crystal display panels

It is shown that thin-film field effect transistors (FETs) made from amorphous (a-) silicon deposited by the glow-discharge technique have considerable potential as switching elements in addressable liquid crystal display panels. The fabrication of the elements and their characteristics with steady and pulsed applied potentials are discussed in some detail. Two important points are stressed: (i) a-Si device arrays can be produced by well-established photolithographic techniques, and (ii) satisfactory operation at applied voltages below 15VV is possible. Small experimental 7×5 transistor panels have been investigated and it is shown that with the present design up to 250-way multiplexing could be achieved. The reproducibility of FET characteristics is good and in tests so far no change has been observed after more than 10⁹ switching operations.     

Fabrication of a graphene field effect transistor array on microchannels for ethanol sensing

A new approach to the fabrication of back-gated graphene FET (field effect transistor) arrays on microchannels was investigated. Narrow walls fabricated on a substrate with SU-8 (a negative photoresist), with top metal electrodes were pressed onto another silicon/SiO₂ substrate with predeposited graphene pieces such that the electrodes came into contact with graphene pieces and formed the source and drain contact. The SU-8 narrow walls with the top metal layer were fabricated by the conventional lift-off process. The graphene pieces were reduced chemically from graphite oxide. The I_DS changed immediately by more than 17% when the device was exposed to an ethanol atmosphere. The current recovered very well after the ethanol gas was pumped out. The SU-8 microchannels served as gas flow passages that helped the ethanol vapor reach the sensitive region of the device: the graphene channel. This work provides a convenient way of constructing back-gated graphene FETs for sensing applications. This method could potentially be scaled up for mass production.     

Theoretic analysis on electric conductance of nano-wire transistors

By employing the commercial software nanoMos and Vienna ab Initio Simulation Package (VASP), the performance of nano-wire field-effect transistors is investigated. In this paper, the Density-Gradient Model (DG Model) is used to describe the carrier transport behavior of the nano-wire transistor under quantum effects. The analysis of the drain current with respect to channel length, body dielectric constant and gate contact work function is presented. In addition, Fermi energy and DOS (Density of State) are introduced to explore the relative stability of carrier transport and electrical conductance for the silicon crystal with dopants. Finally, how the roughness of the surface of the silicon-based crystal is affected by dopants and their allocation can be illuminated by a few broken bonds between atoms near the skin of the crystal.     

Fabrication of a solution-processed thin-film transistor using zinc oxide nanoparticles and zinc acetate

We have fabricated a solution-processed ZnO thin-film transistor without vacuum deposition. ZnO nanoparticles were prepared by the polyol method from zinc acetate, polyvinyl pyrrolidone, and diethyleneglycol. The solution-processable semiconductor ink was prepared by dispersing the synthesized ZnO in a solvent. Inverted stagger type thin-film transistors were fabricated by spin casting the ZnO ink on the heavily doped Si wafer with 200 nm thick SiO₂, followed by evaporation of Cr/Au source and drain electrodes. After the drying and heat treatment at 600 C, a relatively dense ZnO film was obtained. The film characteristics were investigated by scanning electron microscopy (SEM) and X-ray diffraction (XRD). In order to obtain the electrical properties of the solution-derived transistor, the on–off ratio, threshold voltage, and mobility were measured.     

Microcrystalline silicon and micromorph tandem solar cells

“Micromorph” tandem solar cells consisting of a microcrystalline silicon bottom cell and an amorphous silicon top cell are considered as one of the most promising new thin-film silicon solar-cell concepts. Their promise lies in the hope of simultaneously achieving high conversion efficiencies at relatively low manufacturing costs. The concept was introduced by IMT Neuchatel, based on the VHF-GD (very high frequency glow discharge) deposition method. The key element of the micromorph cell is the hydrogenated microcrystalline silicon bottom cell that opens new perspectives for low-temperature thin-film crystalline silicon technology. According to our present physical understanding microcrystalline silicon can be considered to be much more complex and very different from an ideal isotropic semiconductor. So far, stabilized efficiencies of about 12% (10.7% independently confirmed) could be obtained with micromorph solar cells. The scope of this paper is to emphasize two aspects: the first one is the complexity and the variety of microcrystalline silicon. The second aspect is to point out that the deposition parameter space is very large and mainly unexploited. Nevertheless, the results obtained are very encouraging and confirm that the micromorph concept has the potential to come close to the required performance criteria concerning price and efficiency. Received: 1 March 1999 / Accepted: 28 March 1999 / Published online: 1 July 1999     

Ultra‐high long‐term stability of oxide‐TTFTs under current stress

In this letter the stability of transparent thin‐film transistors (TTFTs) based on the ZnO–SnO₂ (ZTO) material system is investigated. Bottom‐gate devices have been subject to electrical stress via a gate–source bias of 10 V and a drain‐source bias of 10 V leading to a drain–source current of 188 µA. In optimized TTFTs with a composition of [Zn]:[Sn] = 36:64 the relative change of the saturated field effect mobility was less than 1% and the threshold voltage shift was about 320 mV after 1000 hours of operation. This extraordinary stability of ZTO TTFTs underlines their suitability as drivers in active matrix OLED displays. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Effect of modifying a methyl siloxane-based dielectric by a polymer thin film for pentacene thin-film transistors

We report on the fabrication of pentacene thin-film transistors (TFTs) utilizing a spun methyl siloxane-based spin-on-glass (SOG) dielectric and show that these devices can give a similar electrical performance as achieved by using pentacene TFTs with a silicon dioxide (SiO₂) dielectric. To improve the electrical performance of pentacene TFTs with the SOG dielectric, we employed a hybrid dielectric of an SOG/cross-linked poly-4-vinylphenol (PVP) polymer. The PVP film was deposited onto the spun SOG dielectric prior to pentacene evaporation, resulting in an improvement of the saturation field effect mobility (μ_sat) from 0.01 cm²/(V s) to 0.76 cm²/(V s). The good surface morphology and the matching surface energy of the SOG dielectric that was modified with the polymer thin film allow the optimized growth of crystalline pentacene domains whose nuclei are embedded in an amorphous phase.     

Polaron and ion diffusion in a poly(3-hexylthiophene) thin-film transistor gated with polymer electrolyte dielectric

Electrolytes are finding applications as dielectric materials in low-voltage organic thin-film transistors (OTFT). The presence of mobile ions in these materials (polymer electrolytes or ion gels) gives rise to very high capacitance (>10 μF/cm²) and thus low transistor turn-on voltage. In order to establish fundamental limits in switching speeds of electrolyte gated OFETs, we carry out in situ optical spectroscopy measurement of a poly(3-hexylthiophene) (P3HT) OTFT gated with a LiClO₄:poly(ethyleneoxide) (PEO) dielectric. Based on spectroscopic signatures of molecular vibrations and polaron transitions, we quantitatively determine charge carrier concentration and diffusion constants. We find two distinctively different regions: at V _G≥−1.5 V, drift-diffusion (parallel to the semiconductor/dielectric interface) of hole-polarons in P3HT controls charging of the device; at V _G<−1.5 V, electrochemical doping of the entire P3HT film occurs and charging is controlled by drift/diffusion (perpendicular to the interface) of ClO₄ ⁻ counter ions into the polymer semiconductor.