Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the context of a high-performance filter bank and a discrete wavelet transform (DWT). The proposed design paradigm is facilitated by a new RNS accumulator structure based on a carry save adder (CSA). The reported methodology also introduces a polyphase filter structure that results in a reduced look-up table (LUT) budget. The 2C-DA and RNS-DA are compared, in the context of a FPL implementation strategy, using a discrete wavelet transform (DWT) filter bank as a common design theme. The results show that the RNS-DA, compared to a traditional 2C-DA design, enjoys a performance advantage that increases with precision (wordlength).     

Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic

Field-programmable logic (FPL), often grouped under the popular name field-programmable gate arrays (FPGA), are on the verge of revolutionizing sectors of digital signal processing (DSP) industry as programmable DSP microprocessor did nearly two decades ago. Historically, FPGAs were considered to be only a rapid prototyping and low-volume production technology. FPGAs are now attempting to move into the mainstream DSP as their density and performance envelope steadily improve. While evidence now supports the claim that FPGAs can accelerate selected low-end DSP applications (e.g., FIR filter), the technology remains limited in its ability to realize high-end DSP solutions. This is due primarily to systemic weaknesses in FPGA-facilitated arithmetic processing. It will be shown that in such cases, the residue number system (RNS) can become an enabling technology for realizing embedded high-end FPGA-centric DSP solutions. This thesis is developed in the context of a demonstrated RNS/FPGA synergy and the application of the new technology to communication signal processing.     

基于小波变换的IC缺陷轮廓曲线分形维估计

硅片表面缺陷轮廓的形状特征对集成电路(IC)成品率预报及故障分析有重要影响。讨论了IC缺陷轮廓所具有的分形特征,利用小波变换对其参数曲线的分形维数进行了估计,估计结果与实际特征相符,从而为缺陷轮廓特征的描述和计算机模拟提供了一条新的途径。     

连续小波变换开关电流电路的实现

提出了一种用开关电流电路实现连续小波变换的方法,将连续小波变换转化为用带通滤波器组对信号进行处理,并用开关电流电路实现该带通滤波器组.文章采用基于第二代开关电流技术的带通滤波器组实现了8通道的Marr小波.仿真结果表明该滤波器组具有恒Q值,且每个带通滤波器的中心频率与理论值大致相符,从而证实了该方法的可行性.     

数模混合电路实现一维模拟小波变换芯片

整个电路采用标准CMOS工艺,采取模块化设计的方法,把数字频率发生器和模拟滤波器部分分开设计。数字频率发生器采用直接数字综合(DDS)的方式,来产生5种不同中心频率(10个通道),简化了传统模拟压控振荡器(VCO)的设计,提高了频率发生器的灵活性;根据精度要求,模拟高斯低通滤波器采用5阶低通滤波器来进行逼近。并论述和讨论了一种用数字和模拟混合集成电路来实现一维模拟输入的连续小波变换(CWT)芯片的方法。     

小波图像编码的硬件实现

设计了二维离散小波变换和快速零树编码的硬件结构,实现了一小波图像编码系统.编写了各个模块的Verilog HDL模型,并进行了仿真和逻辑综合.最后用Altera公司的CPLD对整个编码系统进行了验证.结果表明,设计的硬件结构是正确的,可以用来实现小波图像编码系统.     

连续小波变换VLSI实现综述

小波变换是信号处理、图像压缩和模式识别等诸多领域中一个非常有效的数学分析工具。然而，实时小波变换计算量大，需要专用硬件来实现。连续小波变换的VLSI实现在处理速度、功耗及适用频率范围方面部具有较明显的优势，且实现方法灵活。本文对近年来有关该领域的研究情况作了综合评述，讨论了其中存在的问题，并指出了今后的若干发展方向，特别是瞬时缩展电路技术是实现低电压低功耗小波变换芯片的重要途经之一。     

小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

基于视觉显著性和置乱技术的小波域鲁棒性水印算法

用于版权认证的数字水印技术应满足安全性.鲁棒性和不可见性.为满足此三方面的要求,提出了一种基于视觉显著性和置乱技术的小波域鲁棒性水印算法.算法利用Arnold变换实现水印图像的置乱处理,通过小波空频分解,根据计算载体小波系数显著性指标确定水印的嵌入强度,最后进行小波系数融合嵌入.实验结果表明,文中算法能够抵抗常见攻击手段,具有较高的安全性、鲁棒性和不可见性.     

VHDL Implementation of the Fast Wavelet Transform

In this paper, a VHDL implementation of a decomposition unit based on Mallat's fast Wavelet Transform, which utilizes a two-channel subband coder, is described. The units were simulated, synthesized, and optimized using Mentor^? design tools. The final design was verified with VHDL test benches and Matlab image processing tools. Results of the decomposition for color images validate the design. Utilizing a clock frequency of 25 MHz, a time period of 45 ms was estimated for the decomposition process of a 640 × 480 color image, which makes it feasible for real time video compression. The size of the layout was found to be within 2.5 × 2.5 mm, which suggests a 40 pin-package tiny frame. Paul Salama received the B.Sc. in Electrical Engineering (First Class Honors) from the University of Khartoum in 1991, and the M.S.E.E. and the Ph.D. degrees from Purdue University in 1993 and 1999, respectively. He is currently an Associate Professor at the Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis (IUPUI). His research interests include image and video compression, image processing, Transmission of compressed Video, Ill posed problems, and medical imaging. Dr. Salama is a member of SPIE, Tau Beta Pi, and Eta Kappa Nu. Maher E. Rizkalla received his Ph.D. in Electrical Engineering from Case Western Reserve University, Cleveland, Ohio in 1985. From Jan. 1985 to Sep. 1986, he was a Visiting Scientist at Argonne National Laboratory, Argonne, IL while being a Visiting Assistant Professor at Purdue University Calumet. Since 1986 he has been with the Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis (IUPUI), where he is Professor of Electrical and Computer Engineering. His research interests include solid-state electronics, VLSI design as applied to DSP, electromagnetics, and engineering education. He has published over 100 papers in these areas. He received the outstanding teaching awards in the ECE Department and in the School five times and was the Professor of the Year at Purdue Calumet in 1986. He is the recipient of one NSF grant, and two FIPSE grants, and is COPI of a number of industrial and equipment grants. Dr. Rizkalla is a Senior Member, IEEE, and a Professional Engineer (PE) registered in the State of Indiana. Michael Eckbauer received the M.S.E.E. degree in Electrical Engineering from Indiana University Purdue University Indianapolis (IUPUI) in December 2002. He is currently with GE Medical Systems in Waukesha, Wisconsin.     

基于开关电流技术的连续小波变换的实现方法

开关电流技术是一种新的模拟抽样数据处理技术。开关电流电路具有一般电路不具有的优点，与标准数字CMOS工艺兼容。连续小波变换是分析非平稳信号的有力工具，在信号处理上有广泛的应用。本文提出用开关电流技术实现连续小波变换的方法，并用Matlab仿真证明了其理论可行性。     

用MOS－DYL工艺结构实现模糊逻辑功能

为了在同一芯片上构造一种高速的模糊逻辑单片系统，本文采用电压型ＤＹＬ工艺与电流型ＭＯＳ工艺相结合的方法，设计了９种实现模糊逻辑基本功能的电路，并通过实验证明其可行性。     

基于小波变换和DCT的字符图像特征抽取新方法

从特征矢量的不变性和抗噪性角度,提出了一种基于小波变换(WT)和离散余弦变换(DCT)的字符特征抽取新方法。利用圆周投影算法,把二维的字符图像转换为一维投影。基于WT和DCT的非线性变换,克服了因变形和噪声引起的一维投影的非线性变形失真。通过对识别不同大小、方向及噪声的字符仿真实验和不同特征抽取方法的对比实验,以及对工业标牌字符的识别,表明该特征抽取方法具有尺度和旋转不变性,有较好的抗噪声能力和很好的分类性能。     

高速多级二维IWT的IP核设计与实现

为满足基于整数小波变换（IWT）的高速图像实时处理系统要求,根据提升小波的框架结构,提出一种基于FPGA多级二维整数小波变换核的结构设计与实现方案。该结构通过将边界扩展过程内嵌于变换过程中,且只需要三行数据缓存,即可以实现行和列同时进行滤波变换。整个变换过程插入多级流水线寄存器,进而降低了功耗,减少了所需内存,达到了更高的处理速度和硬件资源利用率。模块采用VHDL语言进行设计,通过在XCVP30FPGA上验证,该IP核能稳定在100MHz时钟频率下,对尺寸大小为1 600×1 200,深度为12bit图像,当二幅图像输出时间间隔大于图像三行数据输出时间,在不需要将图像分割成小块情况下,就可以同步完成对图像的多级IWT,完全满足高速图像实时处理系统需求。     

1M点FFT算法的FPGA设计与实现

采用可编程门阵列（FPGA）实现FFT算法,增加了信号处理的实时性。针对高速宽带信号的谱分析,提出了一种采用FPGA计算1M点FFT的实现方法,并对运算结果进行了测试验证。该成果同样适用于窄带信号的细微特征分析。     

Q-shift复小波的一种新型构造方法及其在图像去噪中的应用

为了提高复小波变换的效率,本文提出了一种设计Q-shift复小波滤波器的新方法。与目前采用多相位矩阵的晶格分解结构得到正交小波的方法不同的是,这里从更为一般的完全重构滤波器组出发寻求满足特定要求的正交小波。不但可以构造出系数更为简单、运算更加方便的小波,而且可以实现任意精度的复小波变换。该方法的可拓展性好,可以很方便的添加如高阶消失矩等限制并简化设计过程。以普遍采用的Q-shift10/10小波为例,利用本文构造的正交小波可将复小波变换中的乘法运算降低到原来的1/3,而加法基本相当,且小波的频率选择性质更好。将其用于图像去噪的实验表明,采用本文构造的小波可以显著提高处理速度并得到更高的峰值信噪比(PSNR)。     

Image Super Resolution Based on Interpolation of Wavelet Domain High Frequency Subbands and the Spatial Domain Input Image

In this paper, we propose a new super‐resolution technique based on interpolation of the high‐frequency subband images obtained by discrete wavelet transform (DWT) and the input image. The proposed technique uses DWT to decompose an image into different subband images. Then the high‐frequency subband images and the input low‐resolution image have been interpolated, followed by combining all these images to generate a new super‐resolved image by using inverse DWT. The proposed technique has been tested on Lena, Elaine, Pepper, and Baboon. The quantitative peak signal‐to‐noise ratio (PSNR) and visual results show the superiority of the proposed technique over the conventional and state‐of‐art image resolution enhancement techniques. For Lena's image, the PSNR is 7.93 dB higher than the bicubic interpolation.     

基于小波变换和HVS的数字水印算法研究

以静止彩色图像为研究对象,结合人类视觉系统模型,提出了一种基于离散小波变换的数字水印算法,该算法选择在原始图像小波变换的低频子带嵌入水印,提高了水印的鲁棒性和不可见性,并对所提出的算法进行了性能分析,实验结果表明,该算法对常见的图像攻击具有较强的鲁棒性。     

用短时傅里叶和小波变换对鸣叫声的时频分析

短时傅里叶和小波变换是信号处理领域的热点研究问题。本文对2类鸣叫声分别进行短时傅里叶和小波变换，以分辨瞬时频率，得到了较好的结果。并根据所得结果，分析比较了这2类变换的特点。