Layer structure variations of ultra-thin HfO2 films induced by post-deposition annealing

To meet challenges for a smaller transistor feature size, ultra-thin HfO₂ high-k dielectric has been used to replace SiO₂ for the gate dielectric. In order to accurately analyze the ultra-thin HfO₂ films by grazing incidence X-ray reflectivity (GIXRR), an appropriate material model with a proper layer structure is required. However, the accurate model is difficult to obtain, since the interfaces between layers of the ultra-thin HfO₂ films are not easily identified, especially when post-deposition annealing process is applied. In this paper, 3.0 nm HfO₂ films were prepared by atomic layer deposition on p-type silicon wafer, and annealed in Ar environment with temperatures up to 1000 °C. The layer structures and the role of the interfacial layer of the films in the post-deposition annealing processes were evaluated by X-ray diffraction and X-ray photoelectron spectroscopy (XPS). The experimental results and analysis showed that layer thicknesses, crystal phases and chemical structures of the ultra-thin HfO₂ films were significantly dependent on annealing temperatures. The binding energy shifts of Hf 4f, O 1s, and Si 2p elements revealed the formation of Hf silicate (Hf-O-Si bonding) with increasing annealing temperatures. Due to the silicate formation and increasing silicon oxide formation, the interface broadening is highly expected. The structure analysis of the GIXRR spectra using the modified material structure model from the XPS analysis confirmed the interfacial broadening induced by the post-deposition annealing.     

Sr/Si(100)表面TiSi2纳米岛的扫描隧道显微镜研究

为了解半导体衬底与氧化物之间存在的相互作用,以及量子尺寸效应对不同再构体的影响,制备了1—2个原子层厚的TiSi₂/Si(100)纳米岛,并使用扫描隧道显微镜(STM)表征手段详细地研究了TiSi₂ /Si(100)纳米岛的电子和几何特性. 结果发现:这些纳米岛表面显示出明显的金属性;其空态STM图像具有典型的偏压依赖性:在高偏压下STM 图像由三聚物形成的单胞构成,并在低偏压下STM 图像显示为密堆积的图案,这些不同的图案反映出不同能量位的态密度有明显差异. 关键词： 2纳米岛')" href="#">TiSi₂纳米岛 Sr/Si(100)表面 扫描隧道显微镜     

Room-temperature fabrication of ultra-thin ZrOx dielectric for high-performance InTiZnO thin-film transistors

In this letter, indium–titanium–zinc–oxide thin-film transistors with zirconium oxide (ZrO_x) gate dielectric were fabricated at room temperature. In the devices, an ultra-thin ZrO_x layer was formed as the gate dielectric by sol–gel process followed by ultraviolet (UV) irradiation. The devices can be operated under a voltage of 4 V. Enhancement mode operations with a high field-effect mobility of 48.9 cm²/V s, a threshold voltage of 1.4 V, a subthreshold swing of 0.2 V/decade, and an on/off current ratio of 10⁶ were realized. Our results demonstrate that UV-irradiated ZrO_x dielectric is a promising gate dielectric candidate for high-performance oxide devices.     

Characteristics of sandwich-structured Al2O3/HfO2/Al2O3 gate dielectric films on ultra-thin silicon-on-insulator substrates

Sandwich-structure Al₂O₃/HfO₂/Al₂O₃ gate dielectric films were grown on ultra-thin silicon-on-insulator (SOI) substrates by vacuum electron beam evaporation (EB-PVD) method. AFM and TEM observations showed that the films remained amorphous even after post-annealing treatment at 950 °C with smooth surface and clean silicon interface. EDX- and XPS-analysis results revealed no silicate or silicide at the silicon interface. The equivalent oxide thickness was 3 nm and the dielectric constant was around 7.2, as determined by electrical measurements. A fixed charge density of 3 × 10¹⁰ cm⁻² and a leakage current of 5 × 10⁻⁷A/cm² at 2 V gate bias were achieved for Au/gate stack /Si/SiO₂/Si/Au MIS capacitors. Post-annealing treatment was found to effectively reduce trap density, but increase in annealing temperature did not made any significant difference in the electrical performance.     

超薄栅氧化层n-MOSFET软击穿后的导电机制

研究了恒压应力下超薄栅氧化层n型金属-氧化物-半导体场效应晶体管（n-MOSFET）软击穿 后的导电机制.发现在一定的栅电压V_g范围内，软击穿后的栅电流I_g符合Fowl er-Nordheim隧穿公式，但室温下隧穿势垒_b的平均值仅为0936eV，远小于S i/Si O₂界面的势垒高度315eV.研究表明，软击穿后，处于Si/SiO₂界 面量子化能级上的 电子不隧穿到氧化层的导带，而是隧穿到氧化层内的缺陷带上._b与缺陷带能 级和电 子所处的量子能级相关；高温下，激发态电子对隧穿电流贡献的增大导致_b逐 渐降低. 关键词： 软击穿 栅电流 类Fowler-Nordheim隧穿 超薄栅氧化层     

动态应力下超薄栅氧化层经时击穿的可靠性评价

实验发现动态电压应力条件下,由于栅氧化层很薄,高电平应力时间内隧穿入氧化层的电子与陷落在氧化层中的空穴复合产生中性电子陷阱,中性电子陷阱辅助电子隧穿.由于每个周期的高电平时间较短(远远低于电荷的复合时间),隧穿到氧化层的电子很少,同时低电平应力时间内一部分电荷退陷,形成的中性电子陷阱更少.随着应力时间的累积,中性电子陷阱达到某个临界值,栅氧化层突然击穿.高电平时形成的陷阱较少和低电平时一部分电荷退陷,使得器件的寿命提高. 关键词： 超薄栅氧化层 斜坡电压 经时击穿     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing(MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing(PDA) times. The equivalent oxide thickness(EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore,the characteristics of SILC(stress-induced leakage current) for an ultra-thin SiO_2/HfO_2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.     

Physical and electrical characteristics of a high-k Yb2O3 gate dielectric

High-k ytterbium oxide (Yb₂O₃) gate dielectrics were deposited on Si substrate by reactive sputtering. The structural features of these films after postdeposition annealing treatment were studied by X-ray diffraction and X-ray photoelectron spectroscopy. It is found that the Yb₂O₃ gate dielectrics annealed at 700 °C exhibit a larger capacitance value, a lower frequency dispersion and a smaller hysteresis voltage in C-V curves compared with other annealing temperatures. They also show negligible charge trapping under high constant voltage stress. This phenomenon is mainly attributed to the decrease in the amorphous silica thickness.     

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO₂ interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO₂ interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f ^1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide.     

NiSi金属栅电学特性的热稳定性研究

研究了NiSi金属栅的各种电学特性及其热稳定性，提出一个物理模型用于解释当形成温度大于500 ℃时NiSi功函数随退火温度升高而增大的现象.测量了不同退火温度形成的NiSi材料的方块电阻，当退火温度大于400 ℃时，方块电阻达到最小，并在400—600 ℃范围内稳定.比较各种温度下形成的NiSi材料X射线衍射谱的变化，说明温度在400—600 ℃范围内NiSi相为最主要的成分.制备了以NiSi为金属栅的金属氧化物半导体电容.通过等效氧化层电荷密度及击穿电场E_bd的分布研 关键词： 金属栅 NiSi 炉退火 快速热退火     

Room temperature fabrication Oxide TFT with Y2O3 as a gate oxide and Mo contact

In this investigation, an operating voltage as low as 5 V has been achieved for Oxide TFT with Y₂O₃ as a gate oxide and a-IGZO as an active layer. The OTFT has been fabricated at room temperature using RF sputter. The mobility and threshold voltages are 11.3 cm²/V s and 3.4 V for the device with W/L = 0.8, respectively. The annealing at 400 °C in N₂ containing 5% H₂ ambient has been utilized to improve the electrical performance of TFT. The on-off current which is determined by gate dielectric has been observed to be 10⁴. It has also been observed that the dielectric properties of gate oxide deteriorate on annealing. The dielectric constant of Y₂O₃ is observed in the range between 5.1 and 5.4 measured on various devices.     

增强型AlGaN/GaN高电子迁移率晶体管高温退火研究

深入研究了两种增强型AlGaN/GaN高电子迁移率晶体管(HEMT)高温退火前后的直流特性变化.槽栅增强型AlGaN/GaN HEMT在500 ℃ N₂中退火5 min后,阈值电压由0.12 V正向移动到0.57 V,器件Schottky反向栅漏电流减小一个数量级.F注入增强型AlGaN/GaN HEMT在 400 ℃ N₂中退火2 min后,器件阈值电压由0.23 V负向移动到-0.69 V,栅泄漏电流明显增大.槽栅增强型器件退火过程中Schottky有效势垒     

Fabrication and characteristics of high-K HfO2 gate dielectrics on n-germanium

This paper reports that the high-K HfO2 gate dielectrics are fabricated on n-germanium substrates by sputtering Hf on Ge and following by a furnace annealing. The impacts of sputtering ambient, annealing ambient and annealing temperature on the electrical properties of high-K HfO2 gate dielectrics on germanium substrates are investigated. Experimental results indicate that high-K HfO2 gate dielectrics on germanium substrates with good electrical characteristics are obtained, the electrical properties of high-K HfO2 gate dielectrics is strongly correlated with sputtering ambient, annealing ambient and annealing temperature.     

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al₂O₃ as the gate dielectric, deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8⁰N-/N+ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties (1×10¹⁴ cm^-2) and low gate-leakage current (I_G = 1 × 10^-3 A/cm^-2@E_ox = 8 MV/cm). Analysis of the current conduction mechanism on the deposited Al₂O₃ gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.     

Oxide reliability improvement controlling microstructures of substrate/oxide and oxide/gate interfaces

For future ULSIs, the oxide reliability problem is a key issue to realize low-power, high-speed devices whilst retaining its reliability. In the MOSFET structure, a gate oxide consists of the substrate/oxide interface, oxide and oxide/gate interface. Therefore, to improve oxide reliability, it is important to control these three component structures individually. In this report, I will describe experiments to control structures of the above two interfaces using: (1) a combination of a closed wet cleaning system and a load-lock oxidation system and (2) an ultra-thin film deposition CVD technique. By controlling these structures, the oxide reliability was improved. Moreover, the interface structure should be carefully controlled in high- k gate dielectrics in future devices.     

Plasma-produced ultra-thin platinum-oxide films for nanoelectronics: physical characterization

We present a detailed experimental characterization of ultra-thin platinum-oxide films formed on metallic Pt surfaces using O₂ plasma treatment. A monotonic consumption of the metallic Pt by the O₂ plasma is demonstrated by electrical resistance measurements of micron-wide, ultra-thin metallic Pt wires for the range of O₂ plasma exposure times explored in this study. Conversely, angle-resolved X-ray photoelectron spectroscopy (AR-XPS) of the plasma-treated Pt reveals that the oxide layer formed on the Pt surface maintains a constant thickness over these exposure times. In combination, these data demonstrate that the O₂ plasma treatment of Pt simultaneously forms and etches an ultra-thin platinum-oxide layer on the Pt surface. In addition, the AR-XPS data also reveals the oxide layer to be composed of two different platinum–oxygen compounds. Detailed analysis demonstrates a stratified structure for the ultra-thin platinum oxide, with the oxide bulk being composed of PtO₂, likely with PtO defects, and the exposed oxide surface being Pt(OH)_y2 terminated after exposure to ambient conditions. The potential utility of using plasma oxidization to form ultra-thin platinum (or other metal) oxide films on nanoscale metal structures for nano- and molecular-electronic applications is discussed, along with other promising applications in technologies such as sensors and catalysts. PACS 61.43.Dq; 68.47.Gh; 68.55.Ac; 68.55.Jk; 73.50.Bk; 73.61.At; 73.63.Nm; 79.60.Dp     

Nitridation of the SiO2/4H-SiC interface studied by surface-enhanced Raman spectroscopy

We employ surface-enhanced Raman spectroscopy (SERS) to investigate the effect of nitridation on interfacial carbon at the SiO₂/4H-SiC interface. These results demonstrate that the interfacial carbon clusters are strongly modified by post-nitridation process and the nitrogen take-up correlates with the reduction in the interface state density.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

0.18μm CMOS工艺栅极氧化膜可靠性的衬底和工艺依存性

用斜坡电压法(Voltage Ramp, V-ramp)评价了0.18μm双栅极 CMOS工艺栅极氧化膜击穿电量(Charge to Breakdown, Q_bd)和击穿电压(Voltage to Breakdown, V_bd). 研究结果表明，低压器件(1.8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小，而高压器件(3.3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大，击穿电压测试值也发现与击穿电量 关键词： 薄氧 可靠性 击穿电压 击穿电量