Strained-Si pMOSFETs on Very Thin Virtual SiGe Substrates

Strained-Si pMOSFETs on very thin relaxed virtual SiGe substrates are presented.The 240nm relaxed virtual Si0.8Ge0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 1e7cm－2.At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/（V·s）.Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.     

薄虚拟SiGe衬底上的应变Si pMOSFETs

成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT-Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe衬底的应变弛豫度为85%,表面平均粗糙度仅为1.02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

RPCVD生长SiGe薄膜及其性能研究

利用应用材料公司外延设备,在Si(001)衬底上,通过RPCVD方式生长出完全应变、无位错的SiGe外延层.通过X射线衍射和原子力显微镜测试技术,得到了外延层Ge摩尔分数、外延层厚度、生长速率以及表面粗糙度等参数,研究了运用RPCVD方法制备的应变SiGe外延层的生长特性以及薄膜特性.结果表明,在660℃所生长的薄膜,其XRD图像均出现了Pendelossung条纹,表明薄膜质量较好.Ge摩尔分数高达16.5%.薄膜表面粗糙度RMS在0.3～0.6nm.     

应变硅n-MOSFET中电子迁移率的增强及其温度特性

采用减压化学气相淀积(RPCVD)技术在弛豫Si_(1-x)Ge_x虚拟衬底上赝晶生长应变硅层,以其为沟道材料制造得到的应变硅n-MOSFET表现出显著的性能提升。研究了通过改变Si_(1-x)Ge_x中Ge的摩尔组分x以改变硅帽层中的应变以及在器件制造流程中通过控制热开销来避免应变硅层发生弛豫等关键问题。在室温下,相对于体硅器件,应变硅器件表现出约87%的低场电子有效迁移率增强,在相同的过驱动电压下,饱和漏端电流增强约72%。在293 K到353 K的温度范围内研究了反型层电子有效迁移率和饱和漏端电流随温度的变化,实验结果表明,当温度升高时应变硅材料的电子迁移率增强倍数保持稳定。     

Measured In-plane hole drift and hall mobility in heavily-doped strained p-type Si1−xGex

Measured in-plane hole drift and Hall mobilities in heavily boron-doped strained Si_1−xGe_x layers are reported. In the range of boron dopings examined (1.5–2.1 × 10¹⁹ cm⁻³), the drift mobility is seen to increase with increasing germanium fraction. The Hall mobility decreases with increasing germanium fraction. Presented at the 1992 EMC, Boston.     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

PbSe外延薄膜空穴迁移率及其声子散射机理

采用分子束外延技术生长了非人为掺杂的PbSe单晶薄膜,研究了薄膜中声予散射对空穴迁移率的影响.并用霍尔效应和变温电阻率测量方法分析了电学特性,得到PbSe薄膜均具有P型导电性,载流予浓度为(5～8)X10^17cm-3,室湿空穴迁移宰为～300em2/(v·s),随湿度降低迁移率增大,77K温度下的迁移率达到3×10^3cm2/(v·s).通过对PbSe薄膜中的载流子散射机理的理论分析,表明在77～295K温度范围内,PbSe的长缴光学波散射是影响载流子迁移率的主要机制.同时,Raman光谱测量显示,在温度≥203K时,不仅观察到了PbSc长纵光学声子散射L0(r),还观察到了其他光学声子的散射,这些观察到的声子散射影响了PbSe的空穴迁移率.     

SiGe/SiHBT异质界面与pn结界面的相对位移的影响

从模拟和实验两方面研究了SiGe/Si HBT发射结中pn结界面和SiGe/Si界面的相对位置对器件的电流增益和频率特性的影响.发现两界面偏离时器件性能会变差.尤其是当pn结位于SiGe/Si界面之前仅几十?就足以产生相当高的电子寄生势垒,严重恶化器件的性能.据此分析了基区B杂质的偏析和外扩对器件的影响以及SiGe/Si隔离层的作用.     

The properties of Si/Si1-xGex films grown on Si substrates by chemical vapor deposition

A growth parameter study was made to determine the proper of a SiGe superlattice-type configuration grown on Si substrates by chemical vapor deposition (CVD). The study included such variables as growth temperature, layer composition, layer thickness, total film thickness, doping concentrations, and film orientation. Si and SiGe layers were grown using SiH₄ as the Si source and GeH₄ as the Ge source. When intentional doping was desired, diluted diborane for p-type films and phosphine for n-type films were used. The study led to films grown at ∼1000°C with mobilities from ∼20 to 40 percent higher than that of epitaxial Si layers and ∼100 percent higher than that of epitaxial SiGe layers grown on (100) Si in the same deposition system for net carrier concentrations of ∼8x10¹⁵ cm^-3 to ∼2x10¹⁷ cm^-3. Enhanced mobilities were found in multilayer (100)-oriented Si/Si_1-xGe_x films for layer thicknesses ≥400A, for film thicknesses >2μm, and for layers with x = 0.15. No enhanced mobility was found for (111)-oriented films and for B-doped multilayered (100)-orlented films. Supported in part by NASA-Langley Research Center, Hampton, VA, Contract NAS1-16102 (R. Stermer & A. Fripp, Contr. Mon.)     

SiGe异质结晶体管技术的发展

以全球信息产业需求及技术发展为背景,回顾了以能带工程为基础的、在现代通信领域得到广泛应用的SiGe异质结晶体管技术的发展历程。介绍了分子束外延、超高真空化学气象淀积和常压化学气象淀积3种典型的SiGe外延技术并对比了这三种技术的优缺点。在此基础上,对SiGe HBT技术进行了分析总结并列举了其典型技术应用。以IBM的SiGe BiCMOS技术为例,介绍了目前主流的SiGe异质结晶体管技术-SiGe BiCMOS技术的研究现状及典型技术产品。最后对正在发展中的SiGe FET技术做了简要介绍。在回顾了SiGe异质结晶体管技术发展的同时,认为未来SiGe异质结晶体管技术的提高将主要依赖于超薄SiGe基区外延技术。     

AlGaAs/GaAs 三角形量子势阱与方形量子阱的界面粗糙散射的比较

We have theoretically studied the mobility limited by interface roughness scattering on two-dimensional electrons gas（2DEG） at a single heterointerface（triangle-shaped quantum well）.Our results indicate that,like the interface roughness scattering in a square quantum well,the roughness scattering at the Al_xGa_1-xAs/GaAs heterointerface can be characterized by parameters of roughness height A and lateral A,and in addition by electric field F.A comparison of two mobilities limited by the interface roughness scattering between the present result and a square well in the same condition is given.     

一种适合制作CMOS的SiGe PMOSFET

在通常适合于制作埋沟SiGe NMOSFET的Si/弛豫SiGe/应变Si/弛豫SiGe缓冲层/渐变Ge组分层的结构上,制作成功了SiGe PMOSFET.这种SiGe PMOSFET将更容易与SiGe NMOSFET集成,用于实现SiGe CMOS.实验测得这种结构的SiGe PMOSFET在栅压为3.5V时最大饱和跨导比用作对照的Si PMOS提高约2倍,而与常规的应变SiGe沟道的器件相当.     

Fully strained Si0.75Ge0.25 epitaxial films with HfSiO gate dielectrics for high mobility channel metal-oxide semiconductor devices

The authors report on fully strained Si_0.75Ge_0.25 metal-oxide-semiconductor capacitors with HfSiO₂ high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si_0.75Ge_0.25 films are directly grown on Si substrates below the critical thickness. HfSiO₂ high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO₂ gate oxides by >100×. Interfacial oxide of the HfSiO₂/Si_0.75Ge_0.25 stack consists primarily of SiO₂ with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO₂/SiGe gate stack.