| Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process |
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| 作者姓名： | 王 源 贾 嵩 陈中建 吉利久 |
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| 作者单位： | Institute of Microelectronics, Peking University, Beijing 100871, China |
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| 摘 要： | A systemic and comprehensive ESD-induced parasitic model is presented in this paper,which is used to analyse the parasitic influences of electrostatic discharge (ESD)protection circuits on the performance of radio frequency applications. A novellow-parasitic ESD protection structure is made in a 0.35mum 1P3M silicide CMOSprocess. The measured results show that this novel structure has a low parasiticcapacitance about 310fF and a low leakage current about 12.2nA with a suitable ESDrobustness target about 5kV human body model.
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| 关 键 词： | 静电放电 射电频率 寄生电容 泄漏电流 |
| 收稿时间： | 2005-12-29 |
| 修稿时间： | 2005-12-292006-06-12 |
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