| Characterization of Al2O3/GaN/AIGaN/GaN metal- insulator-semiconductor high electron mobility transistors with different gate recess depths＊ |
| |
| 作者单位： | [1]School of Technical Physics, Xidian University, Xi＇an 710071, China [2]Key Laboratory for Wide Band-Gap Semiconductor Mater/a/s and Devices, School of Microelectronies, Xidian University, Xi＇an 710071, China |
| |
| 基金项目： | Project supported by the National Key Science and Technology Special Project, China （Grant No. 2008ZX01002-002）, and the National Natural Science Foundation of China （Grant No. 60736033）. |
| |
| 摘 要： | In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal-insulator-semiconductor （MIS） high electron mobility transistors （HEMTs）, we demonstrate better performances of recessed-gate A1203 MIS-HEMTs which are fabricated by Fluorine-based Si3N4 etching and chlorine- based A1CaN etching with three etching times （15 s, 17 s and 19 s）. The gate leakage current of MIS-HEMT is about three orders of magnitude lower than that of A1GaN/CaN HEMT. Through the recessed-gate etching, the transconductanee increases effectively. When the recessed-gate depth is 1.02 nm, the best interface performance with Tit----（0.20--1.59） p~s and Dit ：（0.55-1.08）x 1012 cm-2.eV- 1 can be obtained. After chlorine-based etching, the interface trap density reduces considerably without generating any new type of trap. The accumulated chlorine ions and the N vacancies in the AIGaN surface caused by the plasma etching can degrade the breakdown and the high frequency performances of devices. By comparing the characteristics of recessed-gate MIS-HEMTs with different etching times, it is found that a low power chlorine-based plasma etching for a short time （15 s in this paper） can enhance the performances of MIS-HEMTs effectively.
|
| 关 键 词： | 高电子迁移率晶体管 半导体 绝缘体 金属 HEMT器件 界面陷阱密度 槽深 表征 |
| 本文献已被 维普 等数据库收录！ |
|
