Planar ion chip design for scalable quantum information processing |
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| Authors: | Wan Jin-Yin Wang Yu-Zhu Liu Liang |
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| Affiliation: | Key Laboratory for Quantum Optics, Shanghai Institute ofOptics and Fine Mechanics, Chinese Academy of Sciences, Shanghai201800, China |
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| Abstract: | We investigate a planar ion chip design with a two-dimensional arrayof linear ion traps for scalable quantum information processing.Qubits are formed from the internal electronic states of trapped$^{40}$Ca$^{+}$ ions. The segmented electrodes reside in a singleplane on a substrate and a grounded metal plate separately, acombination of appropriate rf and DC potentials is applied to themfor stable ion confinement. Every two adjacent electrodes cangenerate a linear ion trap in and between the electrodes above thechip at a distance dependent on the geometrical scale and otherconsiderations. The potential distributions are calculated by usinga static electric field qualitatively. This architecture provides aconceptually simple avenue to achieving the microfabrication andlarge-scale quantum computation based on the arrays of trapped ions. |
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| Keywords: | ion traps ion chip quantuminformation processing |
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