低功耗互补传输门绝热逻辑和时序电路的设计

研究了采用二相非交叠功率时钟的绝热触发器及时序电路的设计，介绍了采用二相无交叠功率时钟的互补传输门绝热逻辑（CPAL）电路，并分析了其工作原理．该电路利用nMOS管自举原理对负载进行全绝热驱动，从而减小了电路整体功耗，且CPAL能耗几乎与工作频率无关．提出了性能良好的低功耗绝热D、T和JK触发器，并与其他几种绝热触发器进行功耗比较．给出了绝热时序电路的一般设计方法，并作为实例采用应用绝热D触发器设计了十进制计数器．SPICE程序模拟表明：设计的电路具有正确的逻辑功能及低功耗的优点．

Low-power Complementary Pass-transistor Adiabatic Logic and Sequential Circuits

We present a complementary pass-transistor adiabatic logic （CPAL） for low-power design, which is driven by two-phase AC power supply. The bootstrapped nMOS switch is employed to eliminate non-adiabatic loss on output loads. Its energy dissipation is in less dependency on power-clock frequency. The adiabatic D, T and JK flip-flops are proposed. A synthesis method for adiabatic synchronous sequential circuits is proposed. A practical sequential system based on the proposed adiabatic D flip-flop is verified. SPICE simulations demonstrate that the designed circuits have correct logic function and considerable power saving.