基于互连线电容耦合的SR锁存电路研究

通过对线间电容耦合模型的研究, 提出了一种基于互连线电容耦合的SR锁存电路设计方案. 该方案首先分析互连线间电容耦合关系, 利用MOS管栅极电容模拟互连线电容; 然后利用电容耦合结构与线计算特性, 设计或非逻辑门电路, 在此基础上实现基于互连线电容耦合的SR锁存电路; 最后在TSMC 65nm Spectre环境下仿真验证. 结果表明 所设计的电路逻辑功能正 确, 且具有低硬件开销特性.

Research on SR latch circuit based on interconnected coupling capacitor

With the on-going improvement of integrated circuit technology, there are more and more resources with the on-chip interconnection. By studying the capacitive coupling model between lines, in this paper a design scheme of SR latch circuit is proposed based on interconnected capacitance coupling. Capacitance coupling relationship between interconnected lines is established using MOS gate capacitance to simulate interconnected capacitance, and then using capacitive coupling structure and line calculation characteristics. Through designing or NOR gate, SR is implemented based on interconnected capacitance coupling latch circuit. Finally, the simulation is conducted to verify the proposed design in the TSMC 65nm Spectre environment. The results show that the designed circuit logic function is valid and has low hardware overheads.