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USB3.0接口在数据存储系统中的应用
引用本文:石永亮,张会新,秦丽,崔建利.USB3.0接口在数据存储系统中的应用[J].应用声学,2015,23(3).
作者姓名:石永亮  张会新  秦丽  崔建利
作者单位:中北大学,中北大学,中北大学,中北大学
基金项目:国家高技术研究发展计划(863计划) 课题编号:2011AA040404
摘    要:USB3.0的传输速率最快可达5Gbps,因此,为实现大量数据的快速稳定传输,介绍了一种以FPGA为控制核心,DDR2 SDRAM为高速大容量缓存,USB3.0为记录器与计算机进行数据通信接口的高速数据传输系统,通过模块硬件电路及软件协议实现了数据的高可靠性稳定传输,解决了大容量记录器的数据传输速度瓶颈。经长期试验证明:该接口传输速度可稳定到达150M/s,且数据可靠无误,满足任务设计要求。

关 键 词:USB3.0  DDR2  FPGA  高速数据传输

High-speed data transfer circuit design and implementation based on USB3.0
Zhang Hui-xin,Qin li and Cui Jian-li.High-speed data transfer circuit design and implementation based on USB3.0[J].Applied Acoustics,2015,23(3).
Authors:Zhang Hui-xin  Qin li and Cui Jian-li
Institution:North University of China,National Key Laboratory For Electronic Measurement Technology,Key Laboratory of Instrumentation Science Dynamic Measurement,Ministry of Education,North University of China,National Key Laboratory For Electronic Measurement Technology,Key Laboratory of Instrumentation Science Dynamic Measurement,Ministry of Education,North University of China,National Key Laboratory For Electronic Measurement Technology,Key Laboratory of Instrumentation Science Dynamic Measurement,Ministry of Education,North University of China,National Key Laboratory For Electronic Measurement Technology,Key Laboratory of Instrumentation Science Dynamic Measurement,Ministry of Education
Abstract:The fastest transfer rate of USB3.0 is up to 5Gbps, therefore, to achieve fast and stable transmission of large amounts of data, a high-speed data transmission system was introduced,which regards FPGA as a control core, DDR2 SDRAM for high-speed large-capacity cache, USB3.0 for data communication interface between recorder and computer. By module hardware circuitry and software protocols,it has achieved highly reliable and stable transmission of data, and solved large-capacity data transfer speed bottleneck. The long-term test proved: the interface transfer rate may stably reach to 150M / s, and the data is accurate and reliable, designed to meet the mission requirements.
Keywords:USB3  0  DDR2  FPGA  High-speed  data transmission
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