| 基于USB3.0的高速数据传输电路的设计 |
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| 引用本文： | 程龙,李锦明,杜东海,张少华.基于USB3.0的高速数据传输电路的设计[J].应用声学,2015,23(2). |
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| 作者姓名： | 程龙 李锦明 杜东海 张少华 |
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| 基金项目： | 国家自然科学基金(91123036) |
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| 摘 要： | 针对大容量数据记录器与外围计算机之间的数据通信时间长速度慢的问题,借助USB3.0接口良好的向后兼容性、易于使用性、可热插拔性、传输速度快等特点,设计了以FPGA为主控单元, DDR2 SDRAM作为高速大容量缓存,USB3.0接口作为与计算机进行数据通信接口的高速数据传输电路系统。采用外接I2C接口的EEPROM作为USB3.0接口芯片的启动方式；通过专用的线性稳压器为DDR2提供稳定的参考电压和吸收电流；最后详细介绍了USB3.0接口芯片的固件程序配置和FPGA控制模块的逻辑设计。实验测试结果表明,通过USB3.0接口该系统数据传输速度达到149.29M/S,且数据传输可靠。
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| 关 键 词： | USB3.0 DDR2 SDRAM FPGA 高速数据传输 |
The Design of high-speed data transmission circuits based on USB3.0 |
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| LI Jin-ming,Du Dong-hai and Zhang Shao-hua.The Design of high-speed data transmission circuits based on USB3.0[J].Applied Acoustics,2015,23(2). |
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| Authors: | LI Jin-ming Du Dong-hai and Zhang Shao-hua |
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| Institution: | National Key laboratory for Electronic Measurement Technology,North University of China,Key Laboratory of Instrumentation Science Dynamic Measurement of Ministry of Education,North University of China;National Key laboratory for Electronic Measurement Technology,North University of China,Key Laboratory of Instrumentation Science Dynamic Measurement of Ministry of Education,North University of China;National Key laboratory for Electronic Measurement Technology,North University of China,Key Laboratory of Instrumentation Science Dynamic Measurement of Ministry of Education,North University of China;National Key laboratory for Electronic Measurement Technology,North University of China |
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| Abstract: | According to the problem of the data communication at a reduced rate between the large capacity data recorder and computer peripheral .With the help of USB3.0 interface good backward compatibility, ease of use ,hot pluggable resistance, faster transmission speed, design the high-speed data transmission circuitry which is the FPGA as the control unit, DDR2 SDRAM as a high-speed large-capacity cache, USB3.0 interface as a data communication interface with a computer. using the external I2C interface EEPROM as boot mode of USB3.0 interface chip; through linear regulator for DDR2 provides a stable reference voltage and absorption current; introducing firmware configuration of USB3.0 interface chip and the logic design of FPGA control module. Experimental results show that the data transfer speeds of the system up to 149.29M / S by USB3.0interface, and data transmission is reliable. |
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| Keywords: | USB3 0 DDR2 SDRAM FPGA high-speed data transmission |
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