用于铯芯片级原子钟的4.596 GHz射频源研制

芯片级原子钟主要包括射频模块、物理封装模块以及其他的外围控制模块。射频模块的设计关系到芯片级原子钟的短期稳定度，所以射频模块在芯片级原子钟的设计时是非常重要的一部分。本文利用数字锁相环技术实现频率为4.596 GHz的射频源，射频源由三部分组成，包括小数分频频率综合器、压控振荡器和环路滤波器。数字锁相环具有相位噪声低，频谱稳定度高等特点。此外，由于小数分频频率综合器是可编程的，可以通过配置N分频器与R分频器实现输出频率的快速扫描。与此同时，根据相关公式，可以计算出三阶无源环路滤波器的近似参数值，所设计的环路滤波器具有300 kHz的环路带宽以及55的相位裕度。最后，整个基于数字锁相环技术实现的射频源通过仿真、硬件实现以及测试。测试结果显示，射频源的相位噪声为-74.02 dBc/Hz@300 Hz，符合芯片级原子钟射频源的设计要求。

Development of 4.596 GHz RF source for chip-scale atomic clock

Chip-scale atomic clock (CSAC) mainly includes an RF source, a physics package and other peripheral control circuits. The RF source which is related to the short-term stability of the CSAC plays an important role in CSACs. The technology of digital phase-locked loop is used to realize the 4.596 GHz RF source in this paper. The RF source is made up of three parts, including the fractional-N frequency synthesizer chip, the voltage-controlled oscillator (VCO) and the loop filter. Advantages of digital phase-locked loop used in the microwave signal source are low phase noise and pure spectrum. Furthermore, as the fractional-N frequency synthesizer chip is programmable, the output frequency can be swept by configuring the values of R divider and N divider, making the frequency control of CSACs easy. With the related formula, parameters of the loop filter are calculated approximately, and a loop filter with 300 kHz loop bandwidth and 55 phase margin is designed. Finally, The whole RF source based on the digital phase-locked loop is simulated, fabricated and tested. The result shows that the phase noise of the RF source is -74.02 dBc/Hz at 300 Hz offset, which meets the requirement of the RF source for CSACs.