用于重离子加速器磁铁电源的数字调节器设计

 介绍了兰州重离子加速器冷却储存环上采用高级RISC微处理器(ARM)+现场可编程门阵列(FPGA)+DA/AD技术、状态空间方程方法实现对磁铁电源系统数字调节器的设计，它可以实现5阶及以下各阶的调节控制。运用ARM作为调节控制系统的核心处理器，完成系统的多线程任务处理。电源的精度调节通过FPGA和DA/AD相结合的技术来实现，通过千兆光纤接口实现外接数字信号处理器输入信号的直接传输。同时通过光电隔离器对叠加在输入/输出32 bit数字状态量的干扰脉冲进行抑制。经现场测试该调节器达到了加速器电源系统1×10^-4量级的精度要求，并减少了电源系统的故障恢复时间。

Design of digital adjustor applied to power supply system for HIRFL-CSR

The control of power supply is the key point in the design of HIRFL-CSR system. Based on ARM+FPGA+AD/DA and state-space equation techniques, the design of digital adjustor applied in the power supply system for HIRFL-CSR in Lanzhou is realized. The digital adjustor can accomplish an adjustment control of fifth order and lower. ARM is used as the core of the control system to deal with the multi-threaded task and the precision of power adjustment control is implemented mainly by FPGA and AD/DA techniques. The embedded gigabit fiber interface can transmit the digital signal from external DSP board and the system uses optoelectronic isolator to inhibit interference signals for 32 bit input/output digital signals. Field test has proved that this digital adjustor can meet HIRFL-CSR’s control p