基于CPLD的可选输出CCD驱动时序设计

在分析了CCD器件驱动时序关系的基础上,设计了可选输出的驱动时序发生器.作为卫星上的有效载荷,CCD成像系统可以根据入射能量的多少及探测分辨率的需求,以单像元或像元二合一方式输出.选用复杂可编程逻辑器件(CPLD)作为硬件设计平台,使用VHDL语言对驱动时序发生器进行了硬件描述,采用Maxplus Ⅱ对所设计的驱动时序发生器进行了仿真,针对Altera公司的可编程逻辑器件EPM7128SLC84-7进行适配.系统测试结果表明,所研制的驱动时序发生器可以满足高速CCD成像仪的驱动要求.

Design on Driving Generator Based on CPLD Technology for CCD Camera With Optional Output

Driving schedules have been examined in detail. The driving schedule generator with optional output has been designed for CCD camera. As a load of satellite, CCD camera gives the output signal in mode of single or two-in-one, according to incident energy and exploration resolution request. Complex programmable logic device(CPLD)has been chosen as the hardware design platform, driving schedule generator has been described with VHDL. The designed generator has been successfully fulfilled system simulation with Maxplus Ⅱ software and fitted into EPM7128SLC84-7(a kind of CPLD products that made by Altera).Experiments show that designed generator is suitable for the driving of CCD camera.