| 基于CPLD和Verilog HDL语言的一种线阵CCD驱动时序电路的设计 |
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| 引用本文： | 李汉宇,张庆生,张涛,李健.基于CPLD和Verilog HDL语言的一种线阵CCD驱动时序电路的设计[J].光学技术,2007,33(Z1). |
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| 作者姓名： | 李汉宇 张庆生 张涛 李健 |
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| 摘 要： | 以东芝公司生产的TCD132D型号线阵CCD为例,介绍了一种基于CPLD和Verilog HDL语言的CCD时序驱动电路的设计方法。给出了Verilog HDL语言源代码,采用Modelsim SE等软件实现了功能、时序仿真。实验结果表明,设计符合实际工作需要。
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| 关 键 词： | CCD CPLD Verilog HDL 驱动时序电路 |
Design on driving generator based on CPLD and Verilog HDL for a kind of linable CCD |
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| LI Han-yu,ZHANG Qing-sheng,ZHANG Tao,LI Jian.Design on driving generator based on CPLD and Verilog HDL for a kind of linable CCD[J].Optical Technique,2007,33(Z1). |
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| Authors: | LI Han-yu ZHANG Qing-sheng ZHANG Tao LI Jian |
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| Abstract: | Taking TCD132D made by TOSHIBA Corporation as example,the design method of CCD timing drive circuit based on both CPLD and Verilog hardware disicription language is introduced.Some codes of the Verilog HDL source program are given,both function and timing simulation running on Modelsim SE is presented.As a result,the design is well worked in actual circuit. |
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| Keywords: | CCD CPLD Verilog HDL |
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