一种功控状态保持低功耗C单元设计

提出了一种新的具有状态保持功能的功控低功耗C单元, 该C单元采用高阈值NMOS管作为功控开关, 以减小C单元休眠期间的漏功耗, 并利用交叉耦合的高阈值反相器构成数据保持单元, 保持电路休眠状态时的数据. 版图后仿真结果表明: 该C单元具有正确的逻辑功能, 与传统弱反馈C单元相比, 其漏功耗下降86.6%, 动态功耗下降7.6%, 可在基于功控技术的低功耗异步电路设计中应用.

Design: State Retention C-element Using Power Gating Technique

In CMOS VLSI deign, the power density increases rapidly as the techniques get more complex. To tackle this problem, the low power design has become a critical issue concerned. Asynchronous design where the global clock is replaced by a local communication protocol has the potential power-saving advantages. One of the primitives cells used in asynchronous control circuits is the C-element. In this paper, a new low-power C-Element is proposed with state retention aimed at using the low power asynchronous micropipeline. A high-Vth NMOS transistor is utilized to reduce the leaked power consumption in the sleep mode. The state of the C-Element preserves in the high-Vth cross-coupled inverters during the power-down period. The post-layout simulation results show that the proposed low-power C-Element possesses the correct logic function, and it achieves a reduction of 86.6% on leaked power consumption and 7.6% on the dynamic power consumption compared with the conventional weak feedback C-Element. It may reach the conclusion that the proposed power gating approach is more suitable for low power asynchronous circuits design.