SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics |
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Authors: | CAO Yan-Rong HAO Yue MA Xiao-Hua YU Lei HU Shi-Gang |
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Institution: | School of Microelectronics, Xidian University, Xi'an 710071Key Lab of Wide Band-Gap Semiconductor Materials and Devices, XidianUniversity, Xi'an 710071 |
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Abstract: | Negative bias temperature instability (NBTI) and stress-induced leakage current (SILC) both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1V to 1V is divided into four parts: the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress. |
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Keywords: | 73 40 Qv 85 30 Tv |
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