| Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm—C loop filter |
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| 引用本文： | 黄进芳,刘荣宜,赖文政,石钧纬,许剑铭.Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm—C loop filter[J].中国物理 B,2012,21(8):84210-084210. |
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| 作者姓名： | 黄进芳 刘荣宜 赖文政 石钧纬 许剑铭 |
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| 作者单位： | Department of Electronic Engineering,National Taiwan University of Science and Technology;Chunghwa Telecommunication Laboratory,Chunghwa Telecom.Co. |
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| 基金项目： | Acknowledgement s The authors would like to thank the National Chip Implementation Center （CIC） for the chip fabrication and technical support. |
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| 摘 要： | This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop.The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced.Furthermore,the MASH 1-1-1 sigma-delta(Σ▽) modulator is adopted for performing the fractional division number and hence improves the phase noise as well.Measured results show that the locked phase noise is 114.1 dBc/Hz with lower G m-C bandwidth and 111.7 dBm/C with higher G m-C bandwidth at 1 MHz offset from carrier of 5.68 GHz.Including pads and built-in Gm-C filter,the chip area of the proposed frequency synthesizer is 1.06 mm 2.The output power is 8.69 dBm at 5.68 GHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.
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| 关 键 词： | Gm-C loop filter phase-locked loop PLL voltage-controlled oscillator(VCO) |
| 收稿时间： | 2011-07-10 |
Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm-C loop filter |
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| Huang Jhin-Fang,Liu Ron-Yi,Lai Wen-Cheng,Shin Chun-Wei,Hsu Chien-Ming.Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm-C loop filter[J].Chinese Physics B,2012,21(8):84210-084210. |
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| Authors: | Huang Jhin-Fang Liu Ron-Yi Lai Wen-Cheng Shin Chun-Wei Hsu Chien-Ming |
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| Institution: | a Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 10672, Taiwan, China;b Chunghwa Telecommunication Laboratory, Chunghwa Telecom. Co., Taoyuan 32617, Taiwan, China |
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| Abstract: | This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore the MASH 1-1-1 sigma-delta (Σ Δ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and build-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 GHz and consumes 56 mW with off-chip buffer from 1.8-V supply voltage. |
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| Keywords: | Gm-C loop filter phase-locked loop PLL voltage-controlled oscillator (VCO) |
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