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Devices and architectures for photonic chip-scale integration
Authors:J. Ahn  M. Fiorentino  R. G. Beausoleil  N. Binkert  A. Davis  D. Fattal  N. P. Jouppi  M. McLaren  C. M. Santori  R. S. Schreiber  S. M. Spillane  D. Vantrease  Q. Xu
Affiliation:(1) HP Laboratories, 1501 Page Mill Rd., MS 1123, Palo Alto, CA 94304, USA
Abstract:
Silicon nanophotonics holds the promise of dramatically advancing the state of the art in computing by enabling parallel architectures that combine unprecedented performance and ease of use with affordable power consumption. This paper presents a design study for a many-core architecture called Corona which utilizes dense wavelength division multiplexing (DWDM) for on- and off-chip communication together with the devices which will be needed to implement such a communication infrastructure.
Keywords:PACS 42.82.-m  42.82.Ds  42.82.Bq
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