Locating hot carrier degradation in asymmetric nDeMOS transistors by gated diode technique

In this paper, hot carrier degradation in asymmetric nDeMOS transistors is investigated. For the first time, we found that the worst hot carrier stress condition is at I_g,max, and not at I_b,max and HE stress conditions. The damage regions in transistors upon various hot carrier stress modes are located by using gated diode technique. It is found that the interface traps generation in the gate/n-type graded drain (NGRD) overlap and spacer oxide regions is the dominant mechanism of hot carrier degradation in asymmetric nDeMOS transistors upon various hot carrier stress modes. Furthermore, the bulk silicon damages locating at the p-well and NGRD regions during hot carrier stress must be taken into account, because they lead to a series of issues, such as the increase in I_off current, the off-state breakdown voltage decrease, and so on.