Guard rings: Structures,design methodology,integration, experimental results,and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology |
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| Institution: | 1. CERN, 1210 Geneva 23, Switzerland;2. MIND, Archamps, France;3. Suranaree University of Technology, Nakhon Ratchasima, Thailand;4. University of Cagliari, Cagliari, Italy;5. INFN, Italy;6. University of Utrecht, Utrecht, Netherlands;7. Dongguk and Yonsei University, Seoul, South Korea;8. Pusan National University, Busan, South Korea;9. University of Torino, Torino, Italy;10. Ruprecht-Karls-Universitat Heidelberg, Heidelberg, Germany;11. Technische Universitat Wien, Vienna, Austria;12. Central China Normal University, Wuhan, China;1. School of Microelectronics, Xidian University, Xi’an 710071, China;2. Key Laboratory of Wide Band Gap Semiconductor Technology, Xidian University, Xi’an 710071, China;3. School of Advanced Materials and Nanotechnology, Xidian University, Xi’an 710071, China;1. Centre for Material Science and Nano Devices, Department of Physics and Nanotechnology, SRM University, India;2. Department of Materials Science and Engineering, National Chiao Tung University, Taiwan;3. Department of Electronics and Communication Engineering, Center for Materials Science and Nanodevices, SRM University, India;4. Department of Electronics and Communication Engineering, SKP Engineering College, India |
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| Abstract: | This paper will first focus on the guard ring structures, design methodology, integration, experimental results and analysis. In this paper, the focus will be on test structure design issues, electrical characterization, and computer aided design (CAD) methodologies for advanced digital design, and mixed signal applications. The integration of “parameterized cell” guard ring structures concept into a Cadence™ based design methodology for the construction of electrostatic discharge (ESD) structures, I/O design, and latchup for radio frequency (RF) CMOS and Silicon Germanium technology will be discussed. The importance of the guard ring p-cell allows for evaluation of internal and external latchup, and the ability to verify the presence of the guard ring for whole chip design checking, verification and synthesis will be addressed. Additionally, this independent guard ring concept opens the door for a new methodology for RF design of primitive and hierarchical implementations. |
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