MCML/TG混合结构与三值T门和三值Dlatch电路设计

在深入分析MCML和TG的电路特点后，提出将2种结构结合起来进行数字电路设计的思路.该混合结构主要由MCML和TG共同构成，MCML结构产生控制信号，TG进行信号的传输.并以三值T门和三值D锁存器电路为例，验证了这种设计思路的可行性.通过Hspice软件，采用TSMC 0.18 μm CMOS工艺，供电电压1.8 V，对所设计的电路进行仿真，分析结果表明：电路逻辑功能正确；输入输出高低电平一致，具有较好的电压兼容性；功耗保持MCML结构的优势，基本与频率无关；与传统的CMOS电路相比，取得了较大的延迟优化.

The mixed MCML/TG logic and design of ternary T gate and D-latch circuits

Based on the analysis of the characteristic of the MCML and TG circuits,a combined logic is proposed,and the main unit of the logic is composed of MCML and TG.Moreover,3-T Gate and D-latch circuits are designed to validate the accuracy of the logic.The proposed logic is validated by means of Hspice simulations on a TSMC 0.18 μm CMOS technology.The simulation results show the power dissipation of the MCML/TG circuits are almost independent of clock frequency,the input and output voltage is consistent,and the propagation delay is improved greatly compared with the conventional CMOS circuits.