Operation of thin-film gated SOI lateral PIN photodetectors with gate voltage applied and intrinsic length variation

This paper describes the operation principle of thin-film gated SOI lateral PIN photodetectors, and an analytical model of depletion voltage is presented and validated by two-dimensional Atlas simulations. With gate voltage applied to achieve fully depleted (FD) condition in intrinsic region, the variation of intrinsic length (L_i) on photocurrent and dark current characteristics, sensitivity, and speed is addressed. With L_i between 1 and 10 μm, the simulated results predict internal quantum efficiency (QI) in excess of 95% even near 100% at a 400 nm wavelength. Also, QI can yield over 87% for the long channels. Under FD condition, the total −3 dB frequency value can achieve 16 GHz (19 GHz) for L_i = 1  and 4.1 GHz (6.2 GHz) for L_i = 2 μm with V_K = 1.0 V (2.0 V). And a high ratio of more than 10⁷ between illuminated and dark currents can be yielded for all detectors realized in 0.18 μm SOI CMOS technology.