三值脉冲式JKL触发器设计

锁存器和触发器是时钟系统的基本元件.由于具有硬边沿、低延时等特点,脉冲式触发器比主从触发器越来越受到关注.很多文献对二值脉冲式触发器进行了研究,但是目前对三值CMOS脉冲式触发器的研究并不多.本文从脉冲式触发器的特点出发,提出了单边沿、双边沿三值脉冲式JKL触发器的设计,进一步丰富和完善了多值脉冲式触发器的设计.HSPICE模拟结果表明,提出的三值脉冲式JKL触发器具有正确的逻辑功能和功耗低、延时小的特点.与从传统的主从型和维持阻塞型三值JKL触发器相比,所设计的三值脉冲式JKL触发器电路结构简单,节省了近54.5%的能耗.

Design of ternary pulsed JKL flip-flops

Latches and flip-flops are basic elements of clock system. Pulse-triggered flip-flops are widely used in microprocessors in recent years due to their high performance. And many binary pulse-triggered flip-flops have been developed. Multiple-valued logic (MVL) has well-known potential advantages over binary logic in certain applications because of the increased informational content of its signals. However so far, few ternary pulse-triggered flip-flops have been researched. Pulse-triggered ternary JKL flip-flops were proposed according to the characteristics of pulsed flip-flops in this paper. The design of ternary pulsed flip-flops was further developed and improved. HSPICE simulation showed that the proposed pulsed JKL flip-flops have correct logic function, low power dissipation and small delay. As compared with the conventional ternary JKL flip-flops, the proposed pulsed JKL flip-flops have simpler structure and have improvement of 54.5%～68.2% in power consumption.