GaAs LPE growth and its application to FET |
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Authors: | Y Nanishi K Takahei K Kuroiwa |
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Institution: | Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, 3-9-11 Midori-cho, Musashino-shi, Tokyo 180, Japan |
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Abstract: | Residual impurities and deep levels in the LPE GaAs layers grown by a sliding boat method were studied. Residual impurities were investigated by monitoring oxygen and water vapor contents in the exhaust gas during heat treatment. The results are satisfactorily explained by assuming oxygen as a dominant residual impurity. Electron traps with a density higher than 5 × 1012 cm-3 were not observed in the LPE layers, whereas in VPE layers, 0.82 eV electron traps were always observed. LPE double layers (high purity buffer layer and active layer) were fabricated into FET's. GaAs FET's with a 1 μm gate showed no hysteresis loops in the I–V characteristics and had fairly good high-frequency characteristic (fmax = 70 GHz, NF = 2.4 dB at 10.4 GHz). |
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