Design and FPGA-realization of a self-synchronizing chaotic decoder in the presence of noise

This paper describes requirement for wireless transmission of Chaotic Code Division Multiplexed Access (Chaotic CDMA) and it focuses on real-time synchronization algorithm embedded into electronic programmable device. CDMA with quasi-orthogonal codes is used to allow multi-users to transmit simultaneously in the same channel. Since the channel is shared between all users, the receiver system has to cope with channel noise and overall with interference from other users. As a result, one of the main problems of communication with quasi-orthogonal chaotic codes is to implement a real time decoder in presence of noise. Even if set-membership algorithm are efficient in real time synchronization of chaotic discrete generators in the presence of noise, these algorithms require a large memory resource. In this paper, we propose an evolution of set-membership algorithm toward genetic algorithm to be implemented into electronic programmable device. The advantage of genetic algorithm compared with set-membership algorithm is that they require a fixed size of memory.