Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications |
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| Institution: | 1. Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi, India;2. Electronics and Communication Engineering, Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat, India;3. Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, India;4. Department of Electronics, Maharaja Agrasen College, University of Delhi, New Delhi, India;1. Department of Electrical Engineering, Sciences and Research Branch, Islamic Azad University, Tehran, 1477893855, Iran;2. Department of Electrical Engineering, Shahid Beheshti University, Iran;3. Department of Electrical Engineering, Sharif University of Technology, Iran;1. Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, New Delhi, 110021, India;2. Department of Physics, Motilal Nehru College, University of Delhi, New Delhi, 110021, India;3. Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, New Delhi, 110086, India |
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| Abstract: | This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device. |
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| Keywords: | Dual metal gate engineering Junctionless nanowire MOSFET High-k gate dielectric |
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