Analytical capacitance model for 14 nm Fin FET considering dual-k spacer |
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Institution: | Shanghai Key Laboratory of Multidimensional Information Processing and the Department of Electrical Engineering, East China Normal University, Shanghai 200241, China |
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Abstract: | The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor(Fin FET) device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers. |
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Keywords: | fin field-effect transistor parasitic capacitance model conformal mapping TCAD |
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