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用于像素探测器的高事例率高精度TDC ASIC原型电路的设计与仿真
引用本文:郎子健,高超嵩,秦家军,赵雷,孙向明,安琪.用于像素探测器的高事例率高精度TDC ASIC原型电路的设计与仿真[J].原子核物理评论,2022,39(2):206-214.
作者姓名:郎子健  高超嵩  秦家军  赵雷  孙向明  安琪
作者单位:1.核探测与核电子学国家重点实验室, 中国科学技术大学, 合肥 230026
摘    要:像素探测器因其优异的位置分辨能力在高能粒子物理实验的内径探测器中有着广泛应用,随着应用场景的发展,许多物理实验要求探测器及其读出电子学也具备高精度时间测量的能力。针对像素探测器时间测量的需求,设计完成了一款具备高事例率处理能力、高精度特点的TDC(Time-to-Digital Conversion) ASIC(Application Specific Integrated Circuit) 原型电路,将来可以作为核心组成部分集成到像素探测器前端读出ASIC中。采用粗细结合的方案完成TDC的设计,其中粗时间测量基于计数器实现,细时间测量采用TAC(Time-to-Amplitude Converter)结合ADC(Time-to-Amplitude Converter)的结构实现,基于130 nm工艺完成了原型电路的设计。对TDC进行仿真,仿真结果表明,该电路可以最多处理连续11个事例,相邻事例的最短时间间隔为500 ps,bin size达到了2 ps,DNL(Differential Non-Linearity)小于2.8 ps,时间测量精度好于5 ps RMS。

关 键 词:像素探测器    高事例率    高精度    TDC    ASIC
收稿时间:2021-03-08

Design and Simulation of High Event Rate and High Precision TDC ASIC Prototype for Pixel Detector
Zijian LANG,Chaosong GAO,Jiajun QIN,Lei ZHAO,Xiangming SUN,Qi AN.Design and Simulation of High Event Rate and High Precision TDC ASIC Prototype for Pixel Detector[J].Nuclear Physics Review,2022,39(2):206-214.
Authors:Zijian LANG  Chaosong GAO  Jiajun QIN  Lei ZHAO  Xiangming SUN  Qi AN
Institution:1.State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, China2.Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China3.Key Laboratory of Quark and Lepton Physics(MOE)and College of Physical Science & Technology , Central China Normal University , Wuhan 430079 , China)
Abstract:The pixel detector has been widely used in the inner track detector of high energy particle physics experiments because of its excellent position resolution. With the development of physics experiments, many experiments require detectors and readout electronics to have the capability of high-precision time measurement. To reach the requirement of pixel detectors about the time measurement, a TDC(Time-to-Digital Conversion) ASIC(Application Specific Integrated Circuit) prototype with high event rate processing capability and high precision has been designed. It is expected to be integrated with the front-end readout ASIC of pixel detector as a core component in the future. TDC presented in this paper adopts the combination of coarse and fine measurement, in which the coarse time measurement is based on the counter, and the fine time measurement is implemented by employing the architecture of TAC(Time-to-Amplifier Converter) combined with ADC(Analog-to-Digital Converter). The prototype circuit has been designed based on 130 nm process. TDC has also been simulated, the simulation results indicate that the circuit has the capability processing up to 11 consecutive events in which the time interval between adjacent events is as small as 500 ps, while the bin size of TDC is 2 ps, the DNL (Differential Non-Linearity) is less than 2.8 ps, and the time measurement precision is better than 5 ps RMS.
Keywords:
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