相位式激光测距全数字锁相环控制系统

针对减小相位式激光测距中的误差，介绍了一种基于现场可编程门阵列（FPGA）实现的全数字锁相环（ADPLL）控制系统的技术原理。此系统可以提高相位频率检测器的精度，同时不受温度和电压的影响，大幅降低相位式激光测距在测相过程中的频率误差。系统主要由数字鉴相器、数字滤波器和数字控制振荡器等逻辑设备组成，系统中的信号全部为数字信号。实验结果表明，当FPGA内部的参考信号为40 Hz时，采样周期为0.025 s，滤波器在300 ms达到约5 V的电压饱和状态。ADPLL系统避免了模拟电路中常常遇到的不全传输、寄生能力、温度浮动及老化等问题，并且可以在使用重置器件的情况下运行，因此很容易测试和复原。

Control system of all-digital phase-locked loop for phase-shift laser ranging

This paper introduces an FPGA-based all-digital phase-locked loop(ADPLL) control system for phase-shift laser ranging. The system can improve the accuracy of the phase frequency detector and is immune to the effects of temperature and voltage, thus significantly reducing the frequency error in phase detection of phase-shift laser ranging. It consists of a digital phase detector, a digital filter and a digitally controlled oscillator. When the reference signal generated inside the FPGA is 40 Hz, the sampling period is 0.025 s and the output reaches saturation (about 5 V) after approximately 300 ms. The ADPLL control system avoids the problems often encountered by analog circuits, like incomplete transmission, parasite, temperature fluctuations and aging. Moreover, it is easy to test and reset.