Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS processhave been fabricated and characterized. For the devices with channel lengthof 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V forn-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gaten-MOSFET was 150 times less than that of a conventional planar n-MOSFET.These results demonstrate that groove-gate MOSFETs have excellentcapabilities in suppressing short-channel effects. It is worth emphasizingthat our groove-gate MOSFET devices are fabricated by using a simple processflow, with the potential of fabricating devices in the sub-100nm range.