LaTiO高k栅介质Ge MOS电容电特性及Ti含量优化

采用共反应溅射法将Ti添加到La_2O_3中,制备了LaTiO/Ge金属-氧化物-半导体电容,并就Ti含量对器件电特性的影响进行了仔细研究.由于Ti-基氧化物具有极高的介电常数,LaTiO栅介质能够获得高k值;然而由于界面/近界面缺陷随着Ti含量的升高而增加,添加Ti使界面质量恶化,进而使栅极漏电流增大、器件可靠性降低.因此,为了在器件电特性之间实现协调,对Ti含量进行优化显得尤为重要.就所研究的Ti/La_2O_3比率而言,18.4%的Ti/La_2O_3比率最合适.该比率导致器件呈现出高k值(22.7)、低D_(it)(5.5×10~(11)eV~(-1)·cm~(-2))、可接受的J_g(V_g=1V,J_g=7.1×10~(-3)A·cm~(-2))和良好的器件可靠性.

Electrical properties of LaTiO high-k gate dielectric Ge MOS Capacitor and Ti content optimization

Ti is intentionally added into La₂O₃ to prepare LaTiO gate dielectric Ge metal-oxide-semiconductor (MOS) capacitor with both high k value and good interface quality. In order to examine the effects of Ti content on the electrical properties of the device, LaTiO films with different Ti/La₂O₃ ratios (10.6%, 18.4%, 25.7% and 31.5%) are deposited by reactively co-sputtering Ti and La₂O₃ targets. Capacitance-voltage curves, gate-leakage current properties and high-field stress characteristics of the devices are measured and analyzed. It is found that some electrical properties, such as interface-sate density, gate-leakage current, device reliability and k value, strongly depend on Ti content incorporated into La₂O₃. Ti incorporation can significantly increase the k value: the higher the Ti content, the larger the k value is. The relevant mechanism lies in the fact that higher Ti content leads to an increase of Ti-based oxide in the LaTi-based oxide, because Ti-based oxide has larger k value than La-based oxide. On the contrary, interface quality, gate-leakage current and device reliability deteriorate as Ti content increases because Ti-induced defects at and near the interface increase with Ti content increasing. Of the Ti/La₂O₃ ratios in the examined range, the largest Ti/La₂O₃ ratio is 31.5%, which results in the highest k value of 29.4, the largest gate-leakage current of 9.7×10^-2 A·cm^-2 at V_g=1 V, the highest interface-sate density of 4.5×10¹² eV^-1·cm^-2 and the worst device reliability, while the La₂O₃ film without Ti incorporation exhibits the lowest k value of 11.7, the smallest gate-leakage current of 2.5×10^-3 A·cm^-2 at V_g=1 V, the lowest interface-sate density of 3.3×10¹¹ eV^-1·cm^-2 and the best device reliability. As far as the trade-off among the electrical properties is concerned, 18.4% is the most suitable Ti/La₂O₃ ratio, which leads to a higher k value of 22.7, lower interface-sate density of 5.5×10¹¹ eV^-1·cm^-2, an acceptable gate-leakage current of 7.1×10^-3 A·cm^-2 at V_g=1 V, and a better device reliability. In view of the fact mentioned above, excellent electrical properties could be obtained by setting Ti content to be an optimal value. Therefore, the optimization of Ti content is critical for LaTi-based oxide Ge MOS device preparation.