基于金属氧化物薄膜晶体管的高速行集成驱动电路

本文提出了一种基于非晶铟锌氧化物薄膜晶体管的高速行集成驱动电路,该电路采用输入级复用的驱动结构,一级输入级驱动三级输出级,不仅减少电路输入级2/3晶体管的数量,实现AMOLED或AMLCD显示屏的窄边框显示,而且输入级的工作频率是输出级的1/3,该结构适用于高速驱动电路.电路内部产生了三次电容耦合效应,每一次电容耦合效应都可以提高相应节点的电压,保证了信号完整传输.输出级采用了一个二极管接法的薄膜晶体管,该薄膜晶体管连接了输出级的控制信号和上拉薄膜晶体管的栅极,利用的每一级输出级输出时所产生的电容耦合效应,增加上拉薄膜晶体管的栅极电压,有效地提高电路输出能力和工作速度.仿真表明电路能够输出脉宽达到4μs速度.最后成功地制作了10级行集成驱动电路,包括10级输入级电路和30级输出级电路,负载为R=10k?和C=100pF,实验结果验证,该电路满足4k×8k显示屏在120 Hz刷新频率下的驱动需求.

High speed gate driver circuit basd on metal oxide thin film transistors

This paper presents a new high speed gate driver circuit driven by In-Zn-O thin film transistors. Two methods are employed to improve the speed of this dirver: First, the input stage multiplex structure is adopted, one input stage drives three output stages; this could reduce the quantity of thin film transistors and also could achieve the narrow bezels in the AMOLED or AMLCD displays. Even the work frequency of the input stage becomes 1/3 of the output stage. When the speed of the circuit increass, there is enough time for input stage charging and discharging. So this kind of driver is suitable for high speed driving method. Second, three times the capacitance coupled effect generated in the gate driver can pull up the voltage level of the key nodes in the circuit, ensuring the signal integrity, While the first time the effect generated in the input stage is to reduce the charge time of the cascade signal and improve the speed of input stage. The second time that generated between input stage and output stage contrbutes to the integrity of cascade ouput signal and output control signal. A diode-connected thin film transistor applied to connect the output control signal and the gate of pull-up thin film transistors in output stage generates the three time capacitance coupled effects. Since the capacitance coupled effect can pull up the gate voltage of the pull-up thin film transistors during output period, the driving ability of the pull-up thin film transistors and the working speed could be promoted effectively. Simulation result shows that the capacitance coupled effect of each key node can pull up the voltage level considerably and the gate driver can normally work at the speed of 4 μs. Finally, ten stage gate driver circuits have been fabricated successfully including ten input stages and thirty output stages. The test result shows that the proposed gate driver could work normally with a load of R=5 kΩ and C=100 pF. Furthermore, the high speed test result shows that the output signal pulse width of the circuit is 2 μs meeting the driving demands of the 4 k×8 k display at the frame rate of 120 Hz. The power consumption of the gate dirver circuit is measured in different resolutions under the frame frequencies of 60 and 120 Hz respectively.