A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer |
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| Authors: | Luo Xiao-Rong Wang Yuan-Gang Deng Hao and Florin Udrea |
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| Institution: | Department of Engineering, University of Cambridge, Cambridge, CB3 0FA, UK; State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China; State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;Department of Engineering, University of Cambridge, Cambridge, CB3 0FA, UK |
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| Abstract: | A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI. At a low k value the electric field strength in the dielectric buried layer (EI) is enhanced and a Si window makes the substrate share the vertical drop, resulting in a high vertical breakdown voltage; in the lateral direction, a high electric field peak is introduced at the Si window, which modulates the electric field distribution in the SOI layer; consequently, a high breakdown voltage (BV) is obtained. The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%, respectively, compared with those of the conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect. |
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| Keywords: | silicon-on-insulator low k dielectric electric field breakdown voltage |
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