Optimization of fat tree encoder for ultra high speed analog to digital converter using 45 nanometer technology

The design of high speed, compact and low power fat tree encoder circuits using static CMOS gates is presented. In this paper, we propose a modified 3 bit fat tree encoder (FTE) that can operate in high frequency without a sophisticated circuit structure. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. The study uses complementary metal oxide semiconductor (CMOS) 45 nm-technology. The proposed static design has improved delay and power compared to a conventional ROM encoder circuit implementation. The simulation result indicates that it functions successfully and works at 200-MHz speed. The average power consumption of the circuit under room temperature is 20.7 nW. The total core area is 0.011 mm². As expected, the proposed design can be easily integrated in various kind of digital application.