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Fringe-pattern demodulation using an iterative linear digital phase locked loop algorithm
Authors:Munther A. Gdeisat   David R. Burton  Michael J. Lalor  
Affiliation:aElectronic, Communication and Electrical Engineering Department, Hertfordshire University, Collage Lane, Hatfield, Herts AL10 9AB, UK;bThe General Engineering Research Institute (GERI), Liverpool John Moores University, James Parsons Building Room 114, Byrom Street, Liverpool L3 3AF, UK
Abstract:
A novel technique called an iterative linear digital phase locked loop (DPLL) for fringe-pattern demodulation is presented. The proposed technique has better noise immunity than the basic one-dimensional DPLL algorithms (e.g., conventional and linear DPLLs) because it processes a fringe pattern in two dimensions. In the first iteration of the proposed algorithm, it uses a flat reference to estimate the phase of the fringe pattern. The estimated phase map resulting from the first iteration is smoothed using a moving average window and then it is used as a reference to estimate the phase of the fringe pattern in the second iteration. In the third iteration, the phase map resulting from the second iteration is smoothed and used as a reference to estimate the phase of the fringe pattern in the fourth iteration and so on until the demodulated phase map has a good signal-to-noise ratio.
Keywords:Linear digital phase locked loop   Fringe pattern analysis   Profilometry
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