Improvement of electrical properties of silicon-based thin-film transistors by modifying technological fabrication processes

This paper is a review of technological process evolution associated to electrical performance improvement of silicon-based thin-film transistors (TFTs) that were performed mainly in the GM/IETR laboratory. The main objective in agreement with the fields of applications is to fabricate TFTs at a temperature low enough to be compatible with the substrates, glass substrates in a first place and flexible substrates in a second one, which implies several approaches. In fact, the electrical properties of the TFTs, mainly field-effect mobility of carriers in the channel, I _on/I _off drain current ratio, and subthreshold slope, are strongly dependent on the quality and the nature of the channel material, on the material quality and thus on the density of states at the interface with the gate insulator, and on the quality of the gate insulator itself. All the improvements are directly linked to all these aspects, which means an actual combination of the efforts. For the glass substrate, compatible technology processes such as deposition techniques, or solid phase, or laser crystallizations of active layers were studied and compared. The paper details all these approaches and electrical performances. In addition, some results about the use of a silicon–germanium compound as channel active layer and airgap transistors for which the insulator is released, complete the presentation of the evolution of the silicon-based TFTs during the last twenty years.