The characteristics of solid phase crystallized (SPC) polycrystalline silicon thin film transistors employing amorphous silicon process |
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| Authors: | Won-Kyu Lee Sang-Myeon Han Joonhoo Choi Min-Koo Han |
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| Affiliation: | 1. School of Electrical Engineering, Seoul National University, Seoul 151-742, Republic of Korea;2. LCD Business, Samsung Electronics Company, Yongin-si 449-711, Republic of Korea;1. Colorado Energy Research Institute, Colorado School of Mines, Golden, CO, USA;2. National Center for Photovoltaics, National Renewable Energy Laboratory, Golden, CO, USA;3. Department of Physics and Astronomy, University of Toledo, Toledo, OH, USA;4. Department of Physics, Syracuse University, Syracuse, NY, USA |
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| Abstract: | We investigated the electrical properties of polycrystalline silicon (poly-Si) thin film transistors (TFTs) employing field-enhanced solid phase crystallization (FESPC). An n+ amorphous silicon (n+ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal instead of ion doping. By using C–V measurement method, we could explain the diffused phosphorous ions (P+ ions) on the channel surface caused a negatively shifted threshold voltage (VTH) of ?7.81 V at a drain bias of 0.1 V, and stretched out a subthreshold swing (S) of 1.698 V/dec. This process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process and also offers a better uniformity when compared to the conventional laser-crystallized poly-Si TFT process because of non-laser crystallization. |
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