Abstract: | ![]() The second part of this paper deals with the systolic implementation of the computational kernel for factorial data analysis, defined in Part I, on special-purpose hardware. The framework of the study is that a sequence of different algorithms has to be performed on a unique hardware array. This fact has led us to the design of the programmable systolic array SARDA: this is a triangular array which consists of programmable nodes with local memory and programmable orthogonal connections. |