In-situ SiN combined with etch-stop barrier structure for high-frequency AlGaN/GaN HEMT

The etch-stop structure including the in-situ SiN and AlGaN/GaN barrier is proposed for high frequency applications.The etch-stop process is realized by placing an in-situ SiN layer on the top of the thin AlGaN barrier.F-based etching can be self-terminated after removing SiN,leaving the AlGaN barrier in the gate region.With this in-situ SiN and thin barrier etch-stop structure,the short channel effect can be suppressed,meanwhile achieving highly precisely controlled and low damage etching process.The device shows a maximum drain current of 1022 mA/mm,a peak transconductance of 459 mS/mm,and a maximum oscillation frequency(fmax)of 248 GHz.     

High-frequency enhancement-mode millimeterwave AlGaN/GaN HEMT with an fT/fmax over 100 GHz/200 GHz

Ultra-thin barrier (UTB) 4-nm-AlGaN/GaN normally-off high electron mobility transistors (HEMTs) having a high current gain cut-off frequency (f_T) are demonstrated by the stress-engineered compressive SiN trench technology. The compressive in-situ SiN guarantees the UTB-AlGaN/GaN heterostructure can operate a high electron density of 1.27×10¹³cm^-2, a high uniform sheet resistance of 312.8 Ω /□, but a negative threshold for the short-gate devices fabricated on it. With the lateral stress-engineering by full removing in-situ SiN in the 600-nm SiN trench, the short-gated (70 nm) devices obtain a threshold of 0.2 V, achieving the devices operating at enhancement-mode (E-mode). Meanwhile, the novel device also can operate a large current of 610 mA/mm and a high transconductance of 394 mS/mm for the E-mode devices. Most of all, a high f_T/f_max of 128 GHz/255 GHz is obtained, which is the highest value among the reported E-mode AlGaN/GaN HEMTs. Besides, being together with the 211 GHz/346 GHz of f_T/f_max for the D-mode HEMTs fabricated on the same materials, this design of E/D-mode with the realization of f_max over 200 GHz in this work is the first one that can be used in Q-band mixed-signal application with further optimization. And the minimized processing difference between the E- and D-mode designs the addition of the SiN trench, will promise an enormous competitive advantage in the fabricating costs.     

The Anomalous Effect of Interface Traps on Generation Current in Lightly Doped Drain nMOSFET＇s

The anomalous phenomenon of generation current ICD in the lightly doped drain （LDD） nMOSFET measured under the drain bias VD-step mode is reported. We propose an assumption of activated （A） and frozen （F） traps for the VD-step mode： The A traps contributes to ICD while the F process can make them lose the roles as generation centers. The A and F regions can form the F-A region. The comparison of the F and A regions decides the role of the F-A region. The experiments confirm the assumption.     

Low specific on-resistance GaN-based vertical heterostructure field effect transistors with nonuniform doping superjunctions

A novel Ga N-based vertical heterostructure field effect transistor(HFET) with nonuniform doping superjunctions(non-SJ HFET) is proposed and studied by Silvaco-ATLAS,for minimizing the specific on-resistance(R_(on)A) at no expense of breakdown voltage(BV).The feature of non-SJ HFET lies in the nonuniform doping concentration from top to bottom in the n-and p-pillars,which is different from that of the conventional Ga N-based vertical HFET with uniform doping superjunctions(un-SJ HFET).A physically intrinsic mechanism for the nonuniform doping superjunction(non-SJ) to further reduce R_(on)A at no expense of BV is investigated and revealed in detail.The design,related to the structure parameters of non-SJ,is optimized to minimize the R_(on)A on the basis of the same BV as that of un-SJ HFET.Optimized simulation results show that the reduction in R_(on)A depends on the doping concentrations and thickness values of the light and heavy doping parts in non-SJ.The maximum reduction of more than 51% in R_(on)A could be achieved with a BV of 1890 V.These results could demonstrate the superiority of non-SJ HFET in minimizing R_(on)A and provide a useful reference for further developing the Ga N-based vertical HFETs.     

Effects of Annealing on Schottky Characteristics in A1GaN/GaN HEMT with Transparent Gate Electrode

A1GaN/GaN heterostructure transistors are promising for power and switching applications. In addition, the transparent wide band-gap A1GaN/GaN heterostructure systems have received considerable attention to transparent electronics. Nowdays, Al-doped ZnO （AZO） thin film plays an increas- ingly important role in various fields of transparent electronics.The AZO-gated A1GaN/GaN HEMT with good dc characteristics and frequency character- istics has been reported. Annealing is widely used to improve the electri- cal characteristics of A1GaN/GaN HEMTs. It is re- ported that the Schottky leakage current can be re- duced by over four orders of magnitude by annealing in an A1GaN/GaN heterostructure with ITO/Ni/Au electrode. Pei et al. reported that the transparency of Ni/ITO gates of A1GaN/GaN HEMTs has been sig- nificantly improved after annealing. However, the evaluation of Schottky C V characteristics was ab- sent. Up to now, few results are reported on the Schot- tky annealing characteristics of AZO in A1GaN/GaN HEMT. Thus the effects of annealing on the leakage current, transparency and interface states character- istics need further study.     

Kink effect in current–voltage characteristics of a GaN-based high electron mobility transistor with an AlGaN back barrier

The kink effect in current–voltage(IV)characteristic s seriously deteriorates the performance of a GaN-based HEMT.Based on a series of direct current(DC)IV measurements in a GaN-based HEMT with an AlGaN back barrier,a possible mechanism with electron-trapping and detrapping processes is proposed.Kink-related deep levels are activated by a high drain source voltage(Vds)and located in a GaN channel layer.Both electron trapping and detrapping processes are accomplished with the help of hot electrons from the channel by impact ionization.Moreover,the mechanism is verified by two other DC IV measurements and a model with an expression of the kink current.     

High power-added-efficiency AlGaN/GaN HEMTs fabricated by atomic level controlled etching

An atomic-level controlled etching(ACE)technology is invstigated for the fabrication of recessed gate AlGaN/GaN high-electron-mobility transistors(HEMTs)with high power added efficiency.We compare the recessed gate HEMTs with conventional etching(CE)based chlorine,Cl₂-only ACE and BCl³/Cl₂ACE,respectively.The mixed radicals of BCl₃/Cl₂were used as the active reactants in the step of chemical modification.For ensuring precise and controllable etching depth and low etching damage,the kinetic energy of argon ions was accurately controlled.These argon ions were used precisely to remove the chemical modified surface atomic layer.Compared to the HEMTs with CE,the characteristics of devices fabricated by ACE are significantly improved,which benefits from significant reduction of etching damage.For BCl₃/Cl₂ACE recessed HEMTs,the load pull test at 17 GHz shows a high power added efficiency(PAE)of 59.8%with an output power density of 1.6 W/mm at Vd=10 V,and a peak PAE of 44.8%with an output power density of 3.2 W/mm at Vd=20 V in a continuous-wave mode.     

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.     

透射电子显微镜样品的电解抛光制备方法

在电解抛光过程中用透射和反射光作显微镜观察,借以监视抛光样品,使获得最佳抛光条件。电路中采用了间歇电流装置,使抛光条件更易于控制。样品制备的成功率和重复性有所提高。制备了一些超导材料和非晶质材料的透射电子显微镜样品,拍摄了透射电子显微镜和选区电子衍射照片。 关键词：