基于开关电容阵列ASIC芯片的多通道波形数字化系统设计

基于开关电容阵列（SCA）技术可以实现超高速的波形数字化。本研究是基于实验室设计完成的FEL_SCA芯片进行8通道2 Gsps的波形数字化模块的设计,电路的配置和读出控制功能集成在单个FPGA中完成,此外该模块还包含SDRAM缓存及USB接口。目前已在实验室环境下对其进行了直流电压测试、瞬态波形测试和带宽测试,测试结果表明,在FEL_SCA芯片的输入动态范围100 mV~1 V之间,本波形数字化模块的INL好于1%,通道的RMS噪声约为1.76 mV,带宽约为450 MHz,达到设计目标。Switched Capacitor Arrays (SCAs) can be employed to achieve high speed waveform digitization. In this paper, we designed an 8-channel 2 Gsps waveform digitization module using four SCA chips named FEL_SCA which was designed in our laboratory. In this module, we used a FPGA device for data readout and circuit configuration. Besides, a 128 Mb SDRAM and USB interface were integrated in this module. We have also conducted DC voltage tests, transient tests and bandwidth tests on this module. The results indicate that in the signal voltage range 100 mV~1 V, the INL is better than 1%, the RMS noise is about 1.76 mV and the -3 dB input bandwidth is 450 MHz.     

HIRFL-CSR外靶实验T0探测器前端电子学原型模块设计

介绍了兰州重离子加速器冷却储存环（HIRFL-CSR）外靶实验中时间起点探测器（T0）的前端电子学原型模块的设计与测试。探索了基于过阈时间法和专用集成电路NINO芯片进行多气隙电阻板室探测器信号读出的模拟前端电路的设计技术,并实际完成了原型电子学模块的设计。此模块共集成6个测量通道,可以进行前沿甄别及电荷时间变换。目前已经在实验室条件下完成了各项电子学性能测试,包括不同甄别阈值下的时间精度测试以及不同输入信号幅度下的输出脉宽测试。测试结果表明,在100 fC至2 pC的动态范围内,此模块时间精度好于20 ps,满足应用需求,这也为进一步的电子学系统设计做好了准备。A prototype front end electronics (FEE) module is designed for the T0 detector in the External Experiment in CSR (Cooling Storage Ring) of HIRFL (Heavy Ion Research Facility in Lanzhou). Based on the Time-Over-Threshold method and NINO ASIC, a total of 6 channels are integrated in the module, and both high precision leading edge discrimination and Charge-to-Time Conversion can be achieved, which satisfies the readout requirement of MRPC (Multi-gap Resistive Plate Chamber). A series of tests were also conducted in the laboratory, including time precision tests with different thresholds and output pulse width tests with different input signal amplitudes. Test results indicate that this prototype module functions well, and the time precision is better than 20 ps in the dynamic range from 100 fC to 2 pC, which is beyond application requirement. Through this work, preparation is made for the future readout system design.