基于DFB激光器的光学微波信号的产生

采用量子阱混杂的材料集成技术制备并联分布反馈激光器和Y形波导耦合器集成的新型光电器件.两个并联分布反馈激光器的激射模式在频率上稍有差别,这两束不同频率的激光在Y形波导耦合器拍频产生光学微波信号.分别独立调节注入到两个激光器的电流大小,可以得到从13 GHz到42 GHz连续可调的光学微波信号. 关键词： 光学微波信号生成 分布反馈激光器 Y形波导 拍频     

Analysis on high speed response of a uni-traveling-carrier double hetero-junction phototransistor

In this paper, the positive influence of a uni-traveling-carrier(UTC) structure to ease the contract between the responsivity and working speed of the In P-based double hetero-junction phototransistor(DHPT) is illustrated in detail. Different results under electrical bias, optical bias or combined electrical and optical bias are analyzed for an excellent UTC-DHPT performance. The results show that when the UTC-DHPT operates at three-terminal(3T) working mode with combined electrical bias and optical bias in base, it keeps a high optical responsivity of 34.72 A/W and the highest optical transition frequency of 120 GHz. The current gain of the 3T UTC-DHPT under 1.55-μm light illuminations reaches 62 d B. This indicates that the combined base electrical bias and optical bias of 3T UTC-DHPT can make sure that the UTC-DHPT provides high optical current gain and high optical transition frequency simultaneously.     

应变Si_（1－x）Ge_x层本征载流子浓度和有效态密度的温度特性分析

本文计算了应变Ｓｉ１－ｘＧｅｘ层的本征载流子浓度及导带和价带有效态密度．首次用解析的方法研究了它们与Ｇｅ组份ｘ和温度Ｔ的依赖关系．我们发现，随Ｇｅ组份ｘ的增加，由于Ｓｉ１－ｘＧｅｘ层中应力的影响，导带和价带有效态密度随之快速减少，而本征载流子浓度却随之而近乎指数式地增加．而且，温度Ｔ越低，导带和价带有效态密度随Ｇｅ组份ｘ的增加而减少得越快，而本征载流子浓度上升得越快．同时，我们还发现，具有大Ｇｅ组份ｘ的应变Ｓｉ１－ｘＧｅｘ层，其用Ｓｉ的相应参数归一化的导带和价带有效态密度及它们的积与温度Ｔ的依赖关系弱，而具有小Ｇｅ组份ｘ的应变Ｓｉ１－ｘＧｅｘ层，上述归一化参数与温度Ｔ的依赖关系强，这和目前仅有的文献［８］中它们于温度依赖关系的定性研究结果相一致．本文得到的定量结果对探索应变ＳｉＧｅ层的物理性质、对应变ＳｉＧｅ层基器件的设计、模拟及对低温ＳｉＧｅ器件物理的理解有重要意义．     

基于工艺偏差的自旋转移矩辅助压控磁各向异性磁隧道结电学模型及其应用研究

自旋转移矩辅助电压调控磁各向异性磁隧道结(STT辅助VCMA-MTJ)作为非易失性全加器(NV-FA)中的核心部件,具有切换速度快、功耗低,稳定性好等优点,将在物联网、人工智能等领域具有良好的发展前景.然而随着磁隧道结(MTJ)尺寸的不断缩小以及芯片集成度的不断提高,工艺偏差对MTJ及NV-FA电路性能的影响将变得越来越显著.本文基于STT辅助VCMA-MTJ磁化动力学,在充分考虑薄膜生长工艺偏差以及刻蚀工艺偏差影响的情况下,建立了更为精确的STT辅助VCMA-MTJ电学模型,研究了上述两种工艺偏差对MTJ及NV-FA电路性能的影响.结果表明,当自由层厚度偏差γ_tf≥6%或氧化层厚度偏差γ_tox≥0.7%时,MTJ将无法实现状态切换;当隧穿磁阻率偏差β增大到30%时,读取裕度SM将下降高达17.6%.对于NV-FA电路,通过增大电压V_b1以及写‘0’时增大电压V_b2或写‘1’时减小V_b2,可有效降低非易失性加数写入错误率;通过增大逻辑运算驱动电压V_dd,可...     

Effect of lateral structure parameters of SiGe HBTs on synthesized active inductors

The effect of lateral structure parameters of transistors including emitter width, emitter length, and emitter stripe number on the performance parameters of the active inductor(AI), such as the effective inductance Ls, quality factor Q,and self-resonant frequency ω_0 is analyzed based on 0.35-μm Si Ge Bi CMOS process. The simulation results show that for AI operated under fixed current density JC, the HBT lateral structure parameters have significant effect on Ls but little influence on Q and ω_0, and the larger Ls can be realized by the narrow, short emitter stripe and few emitter stripes of Si Ge HBTs. On the other hand, for AI with fixed HBT size, smaller JCis beneficial for AI to obtain larger Ls, but with a cost of smaller Q and ω_0. In addition, under the fixed collector current IC, the larger the size of HBT is, the larger Ls becomes, but the smaller Q and ω_0 become. The obtained results provide a reference for selecting geometry of transistors and operational condition in the design of active inductors.     

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

The product of the cutoff frequency and breakdown voltage( fT×BVCEO) is an important figure of merit(FOM) to characterize overall performance of heterojunction bipolar transistor(HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator(SOI) Si Ge HBT to simultaneously improve the FOM of fT×BVCEOand thermal stability is presented by using two-dimensional(2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness(TBOX) on fT, BVCEO, and the FOM of fT×BVCEOare presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEOto some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT,BVCEO, and the FOM of fT×BVCEOcan be improved by increasing SOI insulator Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEOis improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI Si Ge HBT overall performance.     

Designing power heterojunction bipolar transistors with non-uniform emitter finger lengths to achieve high thermal stability

With the aid of a thermal-electrical model,a practical method for designing multi-finger power heterojunction bipolar transistors with finger lengths divided in groups is proposed.The method can effectively enhance the thermal stability of the devices without sacrificing the design time.Taking a 40-finger heterojunction bipolar transistor for example,the device with non-uniform emitter finger lengths is optimized and fabricated.Both the theoretical and the experimental results show that,for the optimum device,the peak temperature is lowered by 26.19 K and the maximum temperature difference is reduced by 56.67% when compared with the conventional heterojunction bipolar transistor with uniform emitter finger length.Furthermore,the ability to improve the uniformity of the temperature profile and to expand the thermal stable operation range is strengthened as the power level increases,which is ascribed to the improvement of the thermal resistance in the optimum device.A detailed design procedure is also summarized to provide a general guide for designing power heterojunction bipolar transistors with non-uniform finger lengths.     

应变Si1—xGex层本征载流子浓度和有效态密度的温度特性分析

本计算了应变Ｓｉ１－ｘＧｅｘ层的本征载流子浓度及导带和价带有效态密度。首次用解析的方法研究了它们与Ｇｅ组份ｘ和温度Ｔ的依赖关系。我们发现，随Ｇｅ组份ｘ的增加，由于Ｓｉ１－ｘＧｅｘ层中应力的影响，导带和价带有效态密度随之快速减少，而本征载流子浓度却随之而近乎指数式地增加。而且，温度Ｔ越低，导带和价带有效态密度随Ｇｅ组份ｘ的增加而减少得越快，而本征载流子浓度上升得越快。同时，我们还发现，具有大Ｇｅ组