基于应力集中分析的钻杆内加厚过渡结构设计

通过讨论钻杆内加厚过渡带结构参数对其应力集中系数的影响,提出了实现钻杆内加厚过渡部位低应力集中设计的基本条件,并用钻杆实物疲劳试验对上述分析结果进行了验证,这一工作为改进钻杆内加厚过渡带结构设计提供了重要依据。     

Simulation of the characteristics of low-energy proton induced single event upset

Monte Carlo simulation results are reported on the single event upset (SEU) triggered by the direct ionization effect of low-energy proton. The SEU cross-sections on the 45 nm static random access memory (SRAM) were compared with previous research work, which not only validated the simulation approach used herein, but also exposed the existence of saturated cross-section and the multiple bit upsets (MBUs) when the incident energy was less than 1 MeV. Additionally, it was observed that the saturated cross-section and MBUs are involved with energy loss and critical charge. The amount of deposited charge and the distribution with respect to the critical charge as the supplemental evidence are discussed.     

Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source (CSNS), single event upset (SEU) cross sections of 14 nm fin field-effect transistor (FinFET) and 65 nm quad data rate (QDR) static random-access memories (SRAMs) are obtained under different incident directions of neutrons: front, back and side. It is found that, for both technology nodes, the "worst direction" corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume. The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions. While for multiple-cell upset (MCU) sensitivity, side incidence is the worst direction, with the highest MCU ratio. The largest MCU for the 14 nm FinFET SRAM involves 8 bits. Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.